Siemens ERTEC 200P-2 Manual page 312

1 Data_Set_Ready
2 Data_Carrier_Detect
3 UART_Busy
4 Receive_FIFO_Empty
5 Transmit_FIFO_Full
6 Receive_FIFO_Full
7 Transmit_FIFO_Empty
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
(nUARTCTS) modem status input.
That is, the bit is 1 when the modem
status input is 0.
(DSR) This bit is the complement of
the PrimeCell UART data set ready
0h rh (nUARTDSR) modem status input.
That is, the bit is 1 when the modem
status input is 0.
(DCD) This bit is the complement of
the PrimeCell UART data carrier de-
0h rh tect (nUARTTDCD) modem status
input. That is, the bit is 1 when the
modem status input is 0.
(BUSY) If this bit is set to 1, the
PrimeCell UART is busy transmitting
data. This bit remain set until the com-
0h rh plete byte, including all the stop bits,
has been sent from the shift register.
This bit is set as soon as the transmit
FIFO becomes non-empty.
(RXFE) The meaning of this bit de-
pends on the state of the FEN bit in
the UARTLCR_H register. If the FIFO
1h rh is disabled, this bit is set when the
receive holding register is empty. If the
FIFO is enabled, the RXFE bit is set
when the receive FIFO is empty.
(TXFF) The meaning of this bit de-
pends on the state of the FEN bit in
the UARTLCR_H register. If the FIFO
0h rh is disabled, this bit is set when the
transmit holding register is full. If the
FIFO is enabled, the TXFF bit is set
when the transmit FIFO is full.
(RXFF) The meaning of this bit de-
pends on the state of the FEN bit in
the UARTLCR_H register. If the FIFO
0h rh is disabled, this bit is set when the
receive holding register is full. If the
FIFO is enabled, the RXFF bit is set
when the receive FIFO is full.
(TXFE) The meaning of this bit de-
pends on the state of the FEN bit in
1h rh the UARTLCR_H register. If the FIFO
is disabled, this bit is set when the
transmit holding register is empty. If
312 ERTEC 200P-2 Manual
Version 1.0