Siemens ERTEC 200P-2 Manual page 13

Figure 45: Definition of time reference
Figure 46: MII interface
Figure 47: MDIO interface
Figure 48: Debug interface
Figure 49: ARM926 trace interface
Figure 50: Spike Filter Implementation
Figure 51: Oscillator Circuitry Layout Example
Figure 52: Connection of an external oscillator
Figure 53: Recommended for PLL Power Supply Filter
Figure 54: UTP circuit
Figure 55: FX circuit
Figure 56: FX circuit unused pins
Figure 57: SD level translation circuit
Figure 58: Recommendation for handling special function signals
Figure 59: 400-ball SIP-FPBGA
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Technical data subject to change
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ERTEC 200P-2 Manual
Version 1.0