Memory Management Unit (Mmu); Table 1: Types Of Arm926Ej-S Access To I/D-Tcm / Ahb - Siemens ERTEC 200P-2 Manual

After ARM926-TCM reset, the I/D-TCM is automatically initialized by the HW. The initiali-
zation process (incl. EDC bits) for the complete I/D-TCM takes ca. 16.5 µs. The end of
the initialization process is signaled in the SCRB register 'EDC_INIT_DONE' (see
2.3.10.9.22 ) (I_TCM926_INIT_DONE, D_TCM926_INIT_DONE). The EDC logic can also
X
be disabled using the SCRB register 'EDC_PARITY_EN' (see 2.3.10.9.22
'EDC_DISABLE_ARM926' bit deactivates the EDC logic. The EDC logic is enabled after
reset.
The D-TCM can be written and read by the AHB masters (PN-IP, host interface and
GDMA). Access to the D-TCM by one of these masters stalls the ARM (pipeline paused).
Per word of transfer, this stall usually only lasts for one processor clock cycle to allow
transfer from the 'DMA-DTCM Access Controller' (part of the ARM926 subsystem) to the
D-TCM or vice versa. Arbitration is round robin, i.e. access to the D-TCM is executed
time about by ARM and the 'DMA-DTCM Access Controller'. Arbitration is also carried
again after each individual instance of access for burst transfer.
Table 1 lists the various types of ARM926EJ-S access to I/D-TCM and the AHB and the
potential errors:
EAS 926 , 250 MHz
AHB write AHB read
Memory area access access
ITCM area
(from AHB not possible) na1 na1
ITCM area hole
(from AHB not possible) na1 na1
ITCM area mirror
(not possible) na1 na1
DTCM area ok ok
DTCM area hole
na1 na1
(from AHB not possible)
DTCM area mirror
(not possible) na1 na1

2.3.1.3.3 Memory Management Unit (MMU)

The MMU (see ARM926EJ-S Technical Reference Manual /7/ ) supports a demand page
virtual memory system which may be required by operating systems such as Linux and
ECOS depending on the application. The MMU contains the access protection mecha-
nisms for all memory access. Address translation, access protection and region type are
saved in one TLB (Translation Lookaside Buffer). Separate TLBs are available for instruc-
tion and data. These TLBs are automatically evaluated and updated by the MMU hard-
ware.
Page size: 1 MByte, 64 KByte, 4 KByte and 1 KByte
Separate TLBs for instruction and data
Access attributes can be changed without a TLB flush
A fast context switch enables virtual address remapping in a 0 – 32 MByte area
TLB entries can be locked
The MMU RAMs are not assigned parity.
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
access types
AHB read getting AHB read getting
an ECC detect an ECC error
na1 na1
na1 na1
na1 na1
D-TCM926-1B
+
D-TCM926-2B
D-TCM926-1B
na1 na1
na1 na1

Table 1: Types of ARM926EJ-S access to I/D-TCM / AHB

TCM write TCM read TCM read
access access ECC detect
ok ok I-TCM926-1B
Invalid I- Invalid I-
TCM926 TCM926
Access Access na2
na1 na1 na1
ok ok
D-TCM926-1B
Invalid D- Invalid D-
TCM926 TCM926
Access Access na2
na1 na1 na1
29
). The
X
Description:
TCM read
ECC error
ok no error
I-TCM926-1B
+ not availiable /
I-TCM926-2B na1 access is not possible
not availiable /
access never issues an
na2 na2 ECC detect/error
AHB error response
na1 AHB error via HRESP
D-TCM926-1B AHB ECC detect signal
D-TCM926-1B
+ AHB ECC error signal
D-TCM926-2B 8ns width for the DTCM
D-TCM926-2B
AHB ECC detect signal
na2 I-TCM926-1B 8ns width for the ITCM
AHB ECC error signal
na1 8ns width for the ITCM
I-TCM926-2B
ERTEC 200P-2 Manual
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