Signal Waveforms; Figure 35: Xwd_Out0/ Wd_Int Signal Sequence - Siemens ERTEC 200P-2 Manual

Signal waveforms

2.3.10.2.3
XWD_OUT0
XWD_RES_IN
WDOG0 FFFF_FFFF Reload Count
Load
Run/xStop0
XWD_OUT0
Status_Counter0
INT_WD
WDOG0: Status / counter value for Counter0
FFFF_FFFF = Reset value
Reload = Load value from RELD0 register (reload value)
Count = Countdown
Zero = Counter0 has expired
After a reset, the XWD_OUT0 output is initially logical 0. The XWD_OUT0 output is inac-
tive (=1) only after Counter0 has been started (Run/xStop_Z0=1) and provided the coun-
ter value 0.
If after the start or the last retrigger pulse Counter0 expires after time t1, then
the XWD_OUT0 output becomes active (=0),
the "Status_Counter0" status bit is set and
the INT_WD interrupt signal becomes active (the increasing edge for INT_WD ini-
tiates the interrupt).
A retrigger pulse (Load=1 & Reload-value
causes the status bit and the interrupt signal to be reset.
The XWD_OUT0 output assumes the value logical 1 again only when Counter0 is subse-
quently restarted with a value
t ( RELD0
1
t :
1
RELD0:
T
REF_CLK_IN
T
REF_CLK_IN
t = 0 sec, t
1MIN
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
t
1

Figure 35: XWD_OUT0/ WD_INT signal sequence

0.
) 1 T
REF _ CLK
Time until the counter expires
Decimal value of the reload value for Counter0
: Period duration of the system cycle clock (8 ns).
= 125 MHz:
= 34,36 sec, Interval = 8 ns
1MAX
Reload
Zero Count Zero
t
1
Counter0 = 0
0) or stopping the counter (Run/xStop_Z0=0)
_ IN
263
Reload Count
Clear XWD_OUT0 with
Run/xStop0: 0 1
ERTEC 200P-2 Manual
Version 1.0