Siemens ERTEC 200P-2 Manual page 390

Bit Identifier
7dt0 CDIV_VAL
Register:
Bits:
Description:
Bit Identifier
0 I_TCM926_1B
1 I_TCM926_2B
2 D_TCM926_1B
3 D_TCM926_2B
4 GDMA_1B
5 GDMA_2B
6 PN_1B
7 PN_2B
8 PERIF_1B
9 PERIF_2B
10 I_CACHE_PAR
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Reset
7Ch
EDC_EVENT
31dt0 Reset value: 0h
EDC event register - '0h' must be written to the register to
clear.
Reset
xh
xh
xh
xh
xh
xh
xh
xh
xh
xh
xh
390
Attr. Function / Description
Divider value for determining the bit
rate
fBR = fCLK/(CCR_I2C+1)-
fCLK = fAPB=125 MHz in the I2C
fBR: Bit rate clock (I2C)
r w
fCLK: I2C interface system cycle
clock
for fBR = 1MHz and fCLK=125MHz:
CCR_I2C=124(dec.)
Address: 54h
Attribu-
tes:
Attr. Function / Description
r A 1-bit error has occurred in the I-
w
h TCM of ARM926 and been corrected
r A 2-bit error has occurred in the I-
w
h TCM of ARM926
r A 1-bit error has occurred in the D-
w
h TCM of ARM926 and been corrected
r A 2-bit error has occurred in the D-
w
h TCM of ARM926
r A 1-bit error has occurred in the
w
h GDMA memory and been corrected
r A 2-bit error has occurred in the
w
h GDMA memory
A 1-bit error has occurred in one of
r
w the PN-IP memories and been cor-
h
rected
r A 2-bit error has occurred in one of
w
h the PN-IP memories
r A 1-bit error has occurred in the PerlF
w
h memory and been corrected
r A 2-bit error has occurred in the PerlF
w
h memory
r A parity error has occurred in the I-
w
h cache during reading
rh w
ERTEC 200P-2 Manual
Version 1.0