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After a reset, the XWD_OUT1 output is initially logical 1. The XWD_OUT1 output be-
comes logical 0 and the "Status_Counter1" status bit is set only after Counter1 has been
started (Run/xStop_Z1=1) and the time t2 has expired after the start or the last retrigger
pulse (Load=1).
A retrigger pulse (Load=1 & Reload-value
causes the status bit and the XWD_OUT1 output to be reset again.
t
(
RELD
2
t
:
2
RELD1:
T
REF_CLK_IN
T
REF_CLK_IN
t
= 0 sec, t
2MIN
2.3.10.2.4
Write protection of the watchdog register
If the Watchdog Control/Status register or one of the Watchdog Reload registers is to be
written, a defined bit combination in the upper 16 bits (key bits) must be written simulta-
neously. The key bits are 9876h (arbitrary). The read access returns the value 0000h in
the upper 16 bits.
Starting the Watchdog
2.3.10.2.5
The following sequence describes the initialization phase which at first has to be per-
formed by software:
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Figure 36: XWD_OUT1 signal sequence
1
16
) 1
T
REF
Time until the counter expires
Decimal value of the reload value for Counter1
:
Period duration of the system cycle clock (8 ns)
= 125 MHz:
= 549.76 sec, Interval = 128 ns
2MAX
0) or stopping the counter (Run/xStop_Z1=0)
_
CLK
_
IN
264
ERTEC 200P-2 Manual
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