Siemens ERTEC 200P-2 Manual page 384

1 P1_FX_MODE
5dt2 P1_2_PHY_MODE
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Comment: P1/2_PHYENABLE = 1
triggers a reset extension of 5.2 msec
in the PHY. During this time, the PLL
and all analog and digital components
are started up. Readiness is signaled
in the PHY_Status register with
P1/2_PWRUPRST = 1 (see Figure 37
- FSpec ERTEC 200P).
Comment: When
CONFIG(6..3)="1101", the bit is not
writable and is fixed at the default
value.
1: Enables 100BASE-FX interface
(only useful when P1_PHY_Mode =
r
0010 or 0011
xh w
h
0: The 100BASE-FX interface is ena-
bled
Setting applies to Phy P1 and Phy P2
together.
0000: 10BASE-T HD, Auto-Neg disa-
bled
0001: 10BASE-T FD, Auto-Neg disa-
bled
0010: 100BASE-TX/FX HD, Auto-Neg
disabled
0011: 100BASE-TX/FX FD, Auto-Neg
disabled
0100: 100BASE-TX HD signaled,
Auto-Neg enabled
0101: 100BASE-TX HD signaled,
Auto-Neg enabled, repeater mode
0110: PHY starts in power down
r
mode
xh w
h
0111: Auto-Neg enabled, AutoMDIX
enabled, all possible
1000: All capable. Quick Auto-
Negotiation enabled. Forced Full
Duplex in Parallel Detect mode. Au-
toMDIX enabled. Bits 1 and 0 deter-
mine timing
1001:
1010:
1011:
1100:
1101:
1110:
1111: Loopback mode. The Phy starts
in loopback mode, with the 0.14 bit
384 ERTEC 200P-2 Manual
Version 1.0