Write Access; Figure 15: Emc, Notation Definition For A Write Access (Async) - Siemens ERTEC 200P-2 Manual

Write Access

2.3.5.5.2
CS and WE signals are key to the individual phases in write access. See the write timing
below.
XCS_ASYNC
MA
DQM_SDRAM/XBE
MD
XWE_ASYNC
ASYNC_WAIT
DTXR
XOE_DRIVER
ASYNC_write.vsd

Figure 15: EMC, Notation definition for a write access (ASYNC)

For the asynchronous interface (SRAM), the data are valid until the end of the HOLD
phase.
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Technical data subject to change
SETUP
Write Data
165
STROBE HOLD
111...111
CLK AHB
cycle
ERTEC 200P-2 Manual
Version 1.0