Siemens ERTEC 200P-2 Manual page 271

Six timers
Multiplexers and the corresponding registers for selecting the sources for the inputs of
the TIMER submodules
Clock divider and the corresponding register for activating the clock divider.
The TIMER_TOP module has an APB interface (AMBA 2.0). The access width has to be
32 bits. Different accesses lead to a faulty writing of the register of the TIMER_TOP mod-
ule.
Gate Count Register:
The TIMER_TOP module has a Gate_Trig_Control register in which a SW gate signal
can be set/reset for each TIMER module (= INT_GATE_TRIG_TIM inputs of the TIM-
ERs). The effect depends on the selected mode.
Moreover, the count clock can be released/blocked for each TIMER module (= CLK_EN
inputs of the TIMERs). By writing on this register, all TIMER modules can be started /
stopped synchronously.
Attention: If the SW gate signal is changed while simultaneously the count clock operat-
ing mode is released/blocked, the following behavior applies to all operating modes in
which the SW gate signal is relevant:
a) When blocking the counting pulse:
SW gate signal change has no effect anymore.
b) When releasing the counting pulse:
SW gate signal change is effective in the next count/load clock, depending on the se-
lected operating mode. This also applies to operating modes in which the edge of the
SW gate signal is relevant.
Software event trigger register:
Writing a '1' into the bit "n" of the SW event trigger register triggers a positive edge at the
INT_EV input of the TIMER module "n" and leads to a storing of the counter value of the
TIMER module "n" in the Int_Event register of the TIMER module "n".
The '1' is not stored (read=0).
By writing on this register, the current counter values of all timers can be synchronously
stored in the SW event registers of the TIMER modules.
Multiplexer/TIM_MUX register:
The TIMER_TOP submodule has own multiplexers and registers for their control for each
timer, which serve for selecting the sources for the inputs of the TIMER modules
EXT_GATE_TRIG_TIM, EVENT1, EVENT2. The EXTERNAL_INPUTS (15:0) inputs of
the TIMER_TOP module are available as sources.
The registers for the multiplexers are designed in such a way that the numbers of the
select signals entered there select the corresponding number of the input signal.
Each TIMER module can be assigned own sources for the inputs EXT_GATE_TRIG,
EVENT1, EVENT2.
Thus, versatile measuring tasks can be configured (for examples, see Section "Sequenc-
es").
For the assignment of the input signals of the individual multiplexers, see "Chip/core
level", Subsection "Timer".
clock divider / clock divider register:
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Technical data subject to change
271 ERTEC 200P-2 Manual
Version 1.0