Ahb Master Interface; Apb Slave Interface; Xhif Configuration; Figure 21: Xhif Interface Adjustment - Siemens ERTEC 200P-2 Manual

The driver power of the 1.8 V XHIF pads in the ERTEC 200P is set to 4 mA after power
on. An external host processor should increase this to 9mA for the XHIF pads (configura-
tion in DRIVE95_32GPIO register, see 2.3.10.9.22) before its first read access to the
XHIF interface. 4 mA is enough for the XHIF_XRDY pin as it is wired straight from the
host to the input pin and only needs to recharge this one load.

AHB Master Interface

2.3.6.2.1
The 32-bit data bus supports the AHB-Lite protocol. Erroneous access is indicated by an
interrupt (AHBerror_INT). The lock functionality is not used. Burst access is not support-
ed; only single access over the host interface is permitted.
(The following AHB signals are not used, but set static to HLOCK = "0", HPROT = "0001"
(i.e. DATA_ACCESS), HBURST = "000").

2.3.6.2.2 APB Slave Interface

The HostIF module contains an APB slave interface with a 32-bit data bus and APB pro-
tocol. The 8 pages and the serial interface can be configured over this slave interface.
XHIF configuration parameter assignment is also possible in the HostIF with
XHIF_CONTROL.

2.3.6.2.3 XHIF Configuration

The XHIF configurations (data width, ready polarity and read/write line) for the XHIF-IP
are set with the ConfigPins(5:3) and latched to SCRB_CONFIG_REG when the PowerOn
reset is cleared. ARM926 can also assign parameters for XHIF configuration by changing
the XHIF configurations (data width, ready polarity or read/write line) in
SCRB_CONFIG_REG over the APB interface. The external host should not access
SCRB_CONFIG_REG, as this could cause undefined states at the host interface.
ConfigPin(5) = ConfigPin(4) =
A[22] A[21]
= = not
XHIF_CPU_WIDTH(0)
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note:
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
ConfigPin(3) =
A[20]
= not
XHIF_POL_RDY
XHIF_ACC_MODE
0
1
0
1
0
1
0
1

Figure 21: XHIF interface adjustment

186
XHIF interface
16-bit,
XRDY high-active, XWR only
16-bit,
XRDY high-active, RD-WR separate
16-bit,
XRDY low-active, XWR only
16-bit,
XRDY low-active, RD-WR separate
32-bit,
XRDY high-active, XWR only
32-bit,
XRDY high-active, RD-WR separate
32-bit,
XRDY low-active, XWR only
32-bit,
XRDY low-active, RD-WR separate
ERTEC 200P-2 Manual
Version 1.0