3.3.4 SPI Timing
The frequency of SSPCLK (base frequency for SPI macro): f
3.3.4.1 SPI1
Symbol
Parameter
T
Baudrate
C
T
Valid delay
D
T
Setup Time
S
T
Hold Time
H
T
SFRMIN Setup Time
SFRMS
T
SFRMIN Hold Time
SFRMH
Buffer Driverstrength = 9mA
Based on
1)
C
= 20 pF
L
2)
Ts, Th > 1 x 125 MHz period; Inputs are synchronized with APB-Clock (F
3)
Slave-Mode : SCLK_IN is synchronized in (2 internal clocks)
3.3.4.2 SPI2
Symbol
Parameter
T
Baudrate
C
T
Valid delay
D
T
Setup Time
S
T
Hold Time
H
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
SSPCLK
Min.
Max.
25
-
150
-
-2.9
2.4
21.2
37.7
13.9
-
-14.9
-
-3.8
-
26.7
-
16.7
-
9.6
-
).
SSPCLK
Min.
Max.
25
-
150
-
-3.0
2.2
22.1
36.8
14.6
-
-15.1
-
-4.2
-
26.0
-
468
= 125 MHz.
Unit
Note
ns
Master
ns
Slave
ns
Master
ns
Slave
ns
Master
ns
Slave
ns
Master
ns
Slave
ns
ns
Unit
Note
ns
Master
ns
Slave
ns
Master
ns
Slave
ns
Master
ns
Slave
ns
Master
ns
Slave
ERTEC 200P-2 Manual
Version 1.0