Register Description - Siemens ERTEC 200P-2 Manual

2.3.10.5.3

Register Description

In the description of the UART IP, the read value of the unassigned register bits is in
some cases specified as "unpredictable. A read value of 0 is, however, implemented (see
UartApbif.vhd, assignment to the NextPRDATA signal).
Module: /UART_PL011
Register: UARTDR
Bits: 31dt0
Description:
Bit Identifier
7dt0 Data
8 Framing_Error
9 Parity_Error
10 Break_Error
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Technical data subject to change
Reset value:
UARTDR is the data register
Receive (read) data character
Transmit (write) data character
Reset
00h
0h
0h
0h
310
0h
Attr. Function / Description
Receive (read) data character.
rh w
Transmit (write) data character.
Framing error. When this bit is set to 1,
it indicates that the received character
did not have a valid stop
rh bit (a valid stop bit is 1).
In FIFO mode, this error is associated
with the character at the top of the
FIFO.
Parity error. When this bit is set to 1, it
indicates that the parity of the received
data character does not match the
parity selected as defined by bits 2 and
rh
7 of the UARTLCR_H register.
In FIFO mode, this error is associated
with the character at the top of the
FIFO.
Break error. This bit is set to 1 if a
break condition was detected, indicat-
ing that the received data input
was held LOW for longer than a full-
word transmission time (defined as
start, data, parity and stop bits).
In FIFO mode, this error is associated
rh
with the character at the top of the
FIFO. When a break occurs, only one
0 character is loaded into the FIFO.
The next character is only enabled
after the receive data input goes to a 1
(marking state), and the next valid start
bit is received.
Address: 0h
Attributes: r(h) (w)
ERTEC 200P-2 Manual
Version 1.0