Application Information - Siemens ERTEC 200P-2 Manual

XHIF_CPU_WIDTH(1) is fixed at "0" as an external host with an 8-bit data interface is not
supported.
Description of configuration pins
XHIF_POL_RDY = 0: The XHIF module signals to the host that access with XHIF_XRDY
= 0
1: The XHIF module signals to the host that access with XHIF_XRDY = 1
is complete (ready).
XHIF_ACC_MODE =
XHIF_CPU_WIDTH 00:
01:
10:
The configuration signals are synchronized with the XHIF clock.

2.3.6.2.4 Application Information

The XHIF configurations (16/32-bit data width, ready polarity and read/write line) for the
XHIF-IP are set with a PowerOn reset over ConfigPins 5...3. Subsequent changes can be
made to these configurations by the ARM926EJ-S in the XHIF_CONTROL HostIF regis-
ter over the APB interface.
XHIF_CONTROL should not be changed by the external host. According to the XHIF-IP
specifications, the external host must not address the configuration registers over the
APB interface (AHB2APB bridge). ConfigPins 6..0 may only be set with a PowerOn re-
set.
The external host can only address the internal XHIF-IP page registers (offset, range and
buffer mode) and XHIF_VERSION over the register chip select XHIF_XCS_R. Only the
lowest-value address bits are considered for register selection (address
invalid according to the XHIF-IP spec).
Only halfword write/read access to the registers is permitted with a configured data width
of 16 bits, and only word write/read access with a configured data width of 32 bits. Ac-
cording to the XHIF-IP spec, byte-specific access is not permitted.
When the memory chip select XHIF_XCS_M is active, write/read access is forwarded
straight to the HOSTIF AHB master interface and all aligned access types, byte, halfword
and word, are permitted.
If you configure a 32-bit data width, the XHIF_ADR(1) pin must be clamped to '0' for the
ERTEC 200P (XHIF_ADR(0) internal static setting '0') so that there are always word
addresses internally in the XHIF-IP.
If a data width of 16 bits is configured, the XHIF_ADR(1) pin is required for halfword ad-
dressing and is driven by the external host.
Initialization procedure for XHIF-IP after reset according to IP spec:
- Power on reset cleared
- XHIF configuration with ConfigPins 5...3, thereafter only the ARM926EJ-S can change
configuration
(access by the external host not yet permitted)
- Page setting by ARM926EJ-S: access over the APB to the relevant registers
or page setting by host: access over the XHIF_XCS_R chip select to the relevant
registers
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
is complete (ready).
0: Separate read/write lines are provided
1: A combined read/write signal is used.
16-bit data bus of the external host
32-bit data bus
8-bit data bus
11: Not permitted
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ERTEC 200P-2 Manual
Version 1.0