Siemens ERTEC 200P-2 Manual page 109

bit in the GDMA Error Interrupt State register is set to "1" and the GDMA
interrupt request (DMA_IRQ) is generated.
"Transfer Control" consists of three 2-bit fields: Source Address Mode,
Destination Address Mode and Burst Mode.
The Source Address Mode and Destination Address Mode can be
either "increment" or "hold". Note that the second bit of this field serves
as a reserve bit.
The Burst Mode holds the information about the AHB burst type which
will be used, and can be Single, INCR4, INCR8 and INCR16
(see necessary selection under HW_DMA_REQ signals in chapter 0).
Transfer Count" consists of 4 fields: 1-bit flag "Last Transfer of the Job", 1-
"
bit flag "Enable DMA Acknowledge", 2-bit field "Element Size" and 16-bit
field "Transfer Count".
Last Transfer of the Job - Indicates the last transfer record in a job
(thus the transfers in a job are defined by pointer TRANSFER_PTR in
the Job Control register and the bit "Last Transfer of the Job".) When
no transfer in the Transfer List is marked as the last one, the transfers
will be executed in an infinite loop.
Enable DMA Acknowledge – The output HW_DMA_ACK of a job is set
'1', if the input HW_DMA_REQ of this job is 1, and the bit
HW_FLOW_EN of the job register is 1, and the current transfer is
finished, and the bit DMA_ACK_EN in the Transfer Record is 1. The
output HW_DMA_ACK of a job is reset '0', if the input HW_DMA_REQ
of this job is 0.
Element Size - Sets the size of elements to be copied in the transfer
and can be 8, 16 or 32 bits. The number of bytes to tranfer is (element
size) x (transfer count)
Transfer count - Holds the information on how many elements have to
be copied in this transfer. It can be programmed from 0 to 65535
elements, representing the range of 1 to 65536 elements.
2.3.4.1.3.6 DMA Control registers
The global SW configuration of the GDMA controller is located in the GDMA
Control registers. They are organized in a set of four 32-bit registers: "GDMA
Registers Base Address", "DMA Transfer List Base Address", "GDMA Main
Control" and "Enable Job Counter for the Job".
The DMA Control registers configure the address space of the GDMA registers
and the transfer list as well as control the functions of the GDMA controller, as
described below:
GDMA Registers Base Address (GDMA_REG_ADDR) - Points to the first
address of the GDMA registers. It is used only for comparison purposes.
The DMA destination address is compared with the GDMA registers ad-
dress space to protect the registers against undesirable write accesses by
the GDMA controller, as will be described later.
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Technical data subject to change
109 ERTEC 200P-2 Manual
Version 1.0