Siemens ERTEC 200P-2 Manual page 347

3 LBM
4 SSE
5 MS
6 SOD
Register: SSPDR
Bits: 15dt0
Description: Transmit/Receive FIFO (additional wrapper for bit endianess and parity bit)
Register: SSPSR
Bits: 4dt0
SSPSR is a read-only status register wich contains bits that indicate the FIFO
Description:
fill status and the SSP busy status.
Bit Identifier
0 TFE
1 TNF
2 RNE
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Clearing rhis bit to zero also clears the
SSPRORINTR interrupt if it is already asserted.
1 =Overrun detection is enabled. Overrun condition
generates the SSPRORINTR interrupt.
Loop back mode
0 =Normal serial port operation enabled
0h r w
1 =Output of transmit serial shifter is connected to
input of receive serial shifter internally.
Synchronous serial port enable:
0h r w 0 =SSP operation disabled
1 = operation enabled
Master/slave mode select. This bit can be modified
only when the PrimeCell SSPMS is disabled (SSE
0h r w =0).
0 =Device configured as master (default).
1 =Device configured as slave.
Slave mode output disable.This bis is relevant only in
the slave mode (MS =1). In multiple-slave systems, it
is possible for an SSPMS master to broadcast a
message to all slaves in the system while ensuring
that only the slave drives data onto ist serial output
line. In such systems the RXD lines from multiple
0h r w
slaves could be tied together. To operate in such
systems, the SOD may be set if the SSP slave is not
supposed to drive the SSPTXD line.
0 =SSP may drive the SSPTXD output in slave mode
1 =SSP must not drive the SSPTXD output in slave
mode.
Reset value: 0000h
Reset value: 3h
Reset Attr. Function / Description
1h r Transmit FIFO empty
1h r Transmit FIFO not full
0h r Receive FIFO not empty
347
Address: 8h
Attributes: rh
Address: Ch
Attributes: r
ERTEC 200P-2 Manual
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