Ethernet Phy (Integrated) - Siemens ERTEC 200P-2 Manual

AHB_BurstBreaker(15:8) = 0x08
GDMA Burst_Mode = Single - INCR8
EMC Asyn Memory Banks 0-3 Waits

2.3.8.2 Ethernet PHY (integrated)

A 2-port multiport PHY (Physical Layer Transceiver) that supports 10BASE-T, 100BASE-
TX and 100BASE-FX is integrated into the ERTEC 200P. The interfaces for 10BASE-
T/100BASE-TX and 100BASE-FX are separately for each port and can be set differently.
The PHYs are fully compatible with IEEE802.3 and other standards (ANSI X3.263-1995
and ISO/IEC9314 etc.).
The PHYs are controlled by the PNIP software.
The PHY supports the following functions:
10Base-T/100Base-TX PHY (10 MBd is not supported by ERTEC 200P; the SW
must take account of this)
MII/RMII MAC interface (ERTEC 200P only uses MII)
Support Fiber mode
Auto Cross Over
Auto MDIX
Auto RX polarity in 10BT
Fast link up time
Next Page support
Single Central PLL and BIAS gen
Best in class latency (190ns for Transmit and Receive)
Jitter free Latency
Fast line break detection
TDR based enhanced cable diagnosis
The data interface to the Ethernet MACs is over MII and the management interface is
over the MDIO interface (SMI interface). The clock source is 25 MHz and is provided
either with a 25 MHz quartz at the CLKP_A/B external pins or a 25 MHz external clock
supply at the CLKP_A pin.
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
face, the AHB burst length is to be limited to 8 in the
AHB_ BURSTBREAKER register (default is no limit)
GDMA jobs whose source or destination address
points to an address range of the EMC must be
limited to single, INCR4 or INCR8 in Burst_Mode (i.e.
do not use INCR16)
Access by other masters (ARM926D, ARM926I,
GDMA or HostIF) to EMC asyn memory banks 0-3
delays CPM data transfer to the backplane bus ASIC,
which is also connected to one of the 4 banks. The
wait states of the other 3 banks (either set in the
configuration or created by an external "ready") must
therefore be included in the calculation of the CPM
transfer delay if they are greater than the time re-
quired for an 8-transfer burst to the SDRAM and other
masters access the CPM during CPM data transfer.
235 ERTEC 200P-2 Manual
Version 1.0