Siemens ERTEC 200P-2 Manual page 300

2 TIM_2_INT_GATE_TRIG
3 TIM_3_INT_GATE_TRIG
4 TIM_4_INT_GATE_TRIG
5 TIM_5_INT_GATE_TRIG
6 TIM_0_CLK_EN
7 TIM_1_CLK_EN
8 TIM_2_CLK_EN
9 TIM_3_CLK_EN
10 TIM_4_CLK_EN
11 TIM_5_CLK_EN
31dt12 <reserved>
Register: CLOCK_DIVIDER_REG
Bits: 31dt0
Description:
Bit Identifier
7dt0 CLOCK_DIVIDER_VALUE
8 CLK_DIV_EN
31dt9 <reserved>
Register: EXT_GATE_TRIG_MUX_REG
Bits: 31dt0
Description:
Bit Identifier
3dt0 TIM0_EXT_G_T_SEL_3_0
7dt4 TIM1_EXT_G_T_SEL_3_0
11dt8 TIM2_EXT_G_T_SEL_3_0
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
00000h
Reset value:
Timer Clock Devider Register
Reset
00h
0h
000000h
Reset value:
Timer MUX Register External Gate
Reset
0h
0h
0h
300
1
Software Gate-/Trigger signal Timer
r w
2
Software Gate-/Trigger signal Timer
r w
3
Software Gate-/Trigger signal Timer
r w
4
Software Gate-/Trigger signal Timer
r w
5
r w Clock Enable Timer 0
r w Clock Enable Timer 1
r w Clock Enable Timer 2
r w Clock Enable Timer 3
r w Clock Enable Timer 4
r w Clock Enable Timer 5
not used
00000000h
Attr. Function / Description
r w Clock Divider Value
r w Clock Divider Enable (0 =disabled
not used
00000000h
Attr. Function / Description
Selection of
r w EXTERNAL_INPUTS(15:0) for
EXT_GATE_TRIG of Timer 0
Selection of
r w EXTERNAL_INPUTS(15:0) for
EXT_GATE_TRIG of Timer 1
r w Selection of
Address: C4h
Attributes: (r) (w)
Address: C8h
Attributes: (r) (w)
ERTEC 200P-2 Manual
Version 1.0