Siemens ERTEC 200P-2 Manual page 311

11 Overrun_Error
31dt12 <unused>
Register: UARTRSR_UARTECR
Bits: 31dt0
Description:
Bit Identifier
0 Framing_Error
1 Parity_Error
2 Break_Error
3 Overrun_Error
31dt4 <unused>
Register: UARTFR
Bits: 31dt0
Description:
Bit Identifier
0 Clear_To_Send
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Technical data subject to change
0h
00000h
Reset value:
receive status register/ error clear register
A write to this Register clears the framming, parity, break and over-
run error. The data value is not important.
Reset
0h
0h
0h
0h
0000000h r
Reset value:
flag register; after reset TXFF, RXFF and BUSY are 0, TXFE and
RXFE are 1.
Reset
0h
311
Overrun error. This bit is set to 1 if
data is received and the receive FIFO
is already full.
rh
This is cleared to 0 once there is an
empty space in the FIFO and a new
character can be written to it.
r
0h
Attr. Function / Description
When this bit is set to 1, it indicates
that the received character did not
rh
have a valid stop bit (a valid stop bit is
1).
When this bit is set to 1, it indicates
that the parity of the received data
rh
character does not match the parity
selected in UARTLCR:H (bit 2).
This bit is set to 1 if a break condition
was detected, indicating that the re-
ceived data input was held LOW for
rh
longer than a full-word transmission
time (defined as start, data, parity and
stop bits).
This bit is set to 1 if data is received
and the FIFO is already full.
rh
This bit is cleared to 0 by a write to
UARTECR
Reserved, unpredictable when read.
90h
Attr. Function / Description
(CTS) This bit is the complement of
rh
the PrimeCell UART clear to send
Address: 4h
Attributes: r(h)
Address: 18h
Attributes: r(h)
ERTEC 200P-2 Manual
Version 1.0