Connections On Ertec 200P Toplevel - Siemens ERTEC 200P-2 Manual

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Connections on ERTEC 200P Toplevel

2.3.10.3.7
Timer gate/trigger/event inputs
The timer module has an own multiplexer for each timer for the selection of the sources
for the external timer gate/trigger inputs and the external timer event inputs. The assign-
ment of the sources to the timer multiplexers is stated in the table below.
ATTENTION: Cascading of the timers is only possible when the outputs of the lower-level
timers are connected to the EXT_GATE_TRIG mux of the respective higher-level tim-
er(s)!
ATTENTION: It is expected that all timer inputs/outputs are synchronous with the
timer clock. Asynchronous inputs (e.g. of ASIC pins) have to be synchronized according-
ly. The synchronization of the ASIC pins is done on the core level via two flip-flops each
with125 MHz.
Timer Ext_Gate_Trig_MUX
Timer 0-5 0: TIM_TRIG0 (GPIO6/26)
1: TIM_TRIG1 (GPIO7/27)
2: TIM_TRIG2 (GPIO8)
3: TIM_TRIG3 (GPIO9)
4: TIM_TRIG4 (GPIO10)
5: TIM_TRIG5 (GPIO11)
6: TIM_OUT0 (Timer 0)
7: TIM_OUT2 (Timer 2)
8: TIM_OUT4 (Timer 4)
9: CLK_OUT (clock divider
output timer top)
10: '0'
11: '0'
12: '0'
13: '0'
14: '0'
15: '0'
Tabelle 1 : Table Assignment of the timer gate/trigger/event inputs to the timer multiplexers
With the external inputs TIM_TRIG0-5 it is possible to control the Timers from external
HW. With the internal inputs TIM_OUT0, TIM_OUT2, TIM_OUT4, it is possible to link
timers to each other. The output of the clock divider CLK_OUT in the timer top is con-
nected with bit9 of the input multiplexer.
All six timer outputs (TIM_OUT0-5) are connected to ASIC outputs via GPIOs and the
Interrupt Controller (IRQ21-26) (Kap. 2.3.2.14).
The minimum distance of all signals (Bit0 – Bit15) must be at least 3 x 125MHz clocks
(see chapter 1.3 in Errata-Sheet of Timer_TOP modul /31/). That means e.g. clock divider
value > 3 for CLK_OUT.
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
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Event_1_MUX
0: TIM_TRIG0 (GPIO6/26)
1: TIM_TRIG1 (GPIO7/27)
2: TIM_TRIG2 (GPIO8)
3: TIM_TRIG3 (GPIO9)
4: TIM_TRIG4 (GPIO10)
5: TIM_TRIG5 (GPIO11)
6: TIM_OUT0 (Timer 0)
7: TIM_OUT2 (Timer 2)
8: TIM_OUT4 (Timer 4)
9: CLK_OUT (clock divider
output timer top)
10: '0'
11: '0'
12: '0'
13: '0'
14: '0'
15: '0'
283
Event_2_MUX
0: TIM_TRIG0 (GPIO6/26)
1: TIM_TRIG1 (GPIO7/27)
2: TIM_TRIG2 (GPIO8)
3: TIM_TRIG3 (GPIO9)
4: TIM_TRIG4 (GPIO10)
5: TIM_TRIG5 (GPIO11)
6: TIM_OUT0 (Timer 0)
7: TIM_OUT2 (Timer 2)
8: TIM_OUT4 (Timer 4)
9: CLK_OUT (clock divider
output timer top)
10: '0'
11: '0'
12: '0'
13: '0'
14: '0'
15: '0'
ERTEC 200P-2 Manual
Version 1.0