Siemens ERTEC 200P-2 Manual page 105

2.3.4.1.3.2 Interfaces
The GDMA controller contains the following interfaces:
AHB Slave Interface – Serves for access to the GDMA registers as well as
to the DMA RAM, if the GDMA controller is configured for an internal RAM.
AHB Master Interface – Serves for transferring data via a DMA channel
(read and write accesses). The AHB Master also is used to access the
DMA RAM from the GDMA controller.
Job-starting input signals – Start jobs by HW, they are connected to
PROFINET-IP (3x Application Timer), Timer and GPIO input signals.
Note that start of a job by HW is enabled by means of bit
HW_JOB_START_EN of the Job Control register.
DMA request by HW signals – For a job dedicated to data transfer from a
peripheral, the HW DMA request signal must inform, if data is available on
the peripheral. For a job dedicated to data transfer to the peripheral, the
HW DMA request signal must inform, if the peripheral is ready to receive
the data.
According to these needs, the HW DMA request signals of the GDMA con-
troller are connected to the corresponding outputs of the peripheral devic-
es. The number of DMA request signals is parameterizable and equals to
the
Note that the ready-checking of the peripheral is enabled by means of bit
HW_FLOW_EN of the Job Control register. For every HW DMA request
signal input an HW DMA acknowledge output exists, which is asserted at
the end of a DMA transfer, if this is enabled in the DMA Transfer Record
and the bit HW_FLOW_EN in the job control register is set.
DMA Interrupt Request (DMA_IRQ) output – If a job is finished or a DMA
error occurs (and if the other conditions, described later, are fulfilled), then
the GDMA controller generates a DMA interrupt request.
Error Detection and Correction (EDC) interrupt request – these signals
(GDMA-1B: 1Bit Error corrected, GDMA-2B: 2Bit Error recognized) are
wired to the EDC_EVENT Register in the SCRB Register Block (see chap.
2.3.10.9.22). Addionaly the interrupt 'EDC_Event' IRQ48 is set (see chap.
7.4.1). For the purpose of cleanup the EDC Event Register must be written
with '0h'. By reading the EDC Event Register all Bits are cleared. After Re-
set an initialisation of the EDC-Bits is made. The conclusion of the initiali-
sation can be read in the SCRB Register 'EDC_INIT_DONE' (see chap.
2.3.10.9.22).
These GDMA outputs are internally connected to the outputs of the MEM
Wrapper of the internal DMA RAM. Note that this interrupt is used only
when the GDMA controller is configured for an internal DMA RAM and the
Memory Wrapper is applied.
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Technical data subject to change
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number of jobs.
ERTEC 200P-2 Manual
Version 1.0