Monitoring At The Apb Side; Monitoring At The Emc; Monitoring In The Individual Modules - Siemens ERTEC 200P-2 Manual

2.3.2.5.2 Monitoring at the APB Side

The APB address range is monitored at the APB side. In the event of incorrect address-
ing in the APB address range, access to the APB and AHB side is completed with an
OKAY response as the APB bus is not able to signal the response type.
An IRQ52 interrupt (see 2.3.2.14) is triggered in the ARM interrupt controller. The ad-
dress of the erroneous access is saved in SCRB register QVZ_APB_ADR (see
2.3.10.9.22).
The diagnostic register QVZ_APB_ADR is blocked for subsequent access violations until
it has been read. The master that has triggered the access violation can be read in SCRB
register QVZ_AHB_M.

2.3.2.5.3 Monitoring at the EMC

The external ready signal XRDY_PER is monitored in the EMC. If one of the 4 external
memory areas selected with the output pins XCS_PER(3:0) is addressed, the memory
controller waits for the input signal XRDY_PER (provided ready control is activated in the
corresponding configuration register ASYNC_BANK_x_CONFIG; see 2.3.5.8
edgement delay monitoring is activated in the EXTENDED_CONFIG register (see
2.3.5.8 ) and generates a ready signal internally for the memory controller and IRQ53 (see
X
2.3.2.14 ) in the ARM interrupt controller after a max. of (1048575 + 1) x 16 AHB clock
X
cycles. The duration of monitoring is set in the ASYNC_WAIT_CYCLE_CONFIG register
(see 2.3.5.8 ) (for further information, see 2.3.5.4.5).
X
The address of the erroneous access is also saved in the EMC register AT_ADDR.

2.3.2.5.4 Monitoring in the Individual Modules

Implementation within the modules (IPs)
The following modules:
PN-IP (Profinet-IP)
PER-IF (peripheral interface)
I-filter
Host IF (host interface)
SCRB
have monitoring for unassigned addresses. Access over the AHB and APB that address-
es an undefined address range within a module (IP):
returns read data 0x0000 if READ
is ignored if WRITE.
Access is always completed with READY (AHB OK response) at the APB. At the AHB,
RD access results in an AHB error response; write access is always acknowledged with
an AHB OK response because of the posted behavior of the AHB slave interface.
The first instance of erroneous access is also saved in the module register and output as
a separate output signal with the event
Access_Error has not been released for subsequent erroneous access by the SW
(ERR_LOCK = '0'), all subsequent instances of access are processed without being
saved in the register and without interrupts being output.
An entry in the module register Access_Error is saved when ERR_LOCK = '0' in the fol-
lowing cases:
Write access to read-only registers
Write and read access to address gaps in register and RAM address ranges
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
. As long as the module register
access_err_irq_o
52
). Acknowl-
X
ERTEC 200P-2 Manual
Version 1.0