Pn-Ip Timing; Mii Timing; Mii Timing At Integrated Phy; Mdio Timing - Siemens ERTEC 200P-2 Manual

3.3.3 PN-IP Timing

3.3.3.1 MII Timing

In the receive path, the data are output by the PHY following a rising RX_CLK clock edge.
The PHY guarantees a setup and hold time of 10 ns. This means that the PHY can output
the receive signals with a delay of 10 ns to 30 ns.
In the transmit path, the transmit signals are output by the MAC following a TX_CLK rising
edge. The MAC can output these data with a delay of 0 ns to 25 ns in accordance with the
standard.

3.3.3.1.1 MII Timing at Integrated PHY

Symbol Parameter
T Setup Zeit TX
SU_TX
T Hold Zeit TX
H_TX
T Setup Zeit RX
SU_RX
T Hold Zeit RX
H_RX
Based on

3.3.3.2 MDIO Timing

The management interface has very relaxed timing and is based on a clock frequency of
2.5 MHz. The PHY can output the data with a delay of 0 ns to 300 ns. The MAC must
output the data with a minimum delay of 10 ns and must have output the data within
390 ns at the latest.
A PHY reset implements a hardware reset for all connected PHYs. The timing of this sig-
nal is asynchronous.
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
RX_CLK
RXD(3:0)
RX_DV
RX_ER
TX_CLK
MAC
TXD(3:0)
TX_EN
TX_ER

Figure 46: MII interface

Min.
28.7
3.9
12.3
0
MD_CLK
MAC MDIO
XRES_PHY

Figure 47: MDIO interface

464
PHY
Max. Unit Note
TX_CLK
ns
TX_CLK
ns
RX_CLK
ns
RX_CLK
ns
PHY
ERTEC 200P-2 Manual
Version 1.0