Table Of Contents - Siemens ERTEC 200P-2 Manual

Table of contents

1 INTRODUCTION ......................................................................................................... 15
1.1 Overview of the ERTEC 200P ........................................................................................................15
1.1.1 Mechanisms for PROFINET IO (NRT communication) .............................................................15
1.1.2 Mechanisms for PROFINET IO (RT communication) RTC1/2 ...................................................15
1.1.3 Mechanisms for PROFINET IO (IRT communication) RTC3 .....................................................15
1.1.4 Mechanisms for PROFINET IO (IRT High Performance communication) RTC3 ........................16
1.2 ERTEC 200P data ..........................................................................................................................17
1.2.1 System Reliability ....................................................................................................................18
1.2.2 Electromagnetic Compatibility (EMC) .......................................................................................18
1.3 ERTEC 200P Use Cases ................................................................................................................19
1.3.1 Use Case 1 (UC1): Operation with external host ......................................................................19
1.3.2 Use Case 2 (UC2): Operation without external Host .................................................................20
1.4 Application notes ..........................................................................................................................21
1.4.1 EMC SDRAM Interface ............................................................................................................21
1.4.2 EMC Burst Flash Interface .......................................................................................................22
1.4.3 No free-running frequency at quartz break ...............................................................................22
1.4.4 16-bit Data Access over XHIF in Buffered Mode .......................................................................23
2 DESCRIPTION OF FUNCTIONS ................................................................................ 24
2.1 Block diagram ...............................................................................................................................24
2.2 General Function Description (Motivation) ..................................................................................24
2.3 Description of Individual ERTEC 200P Blocks .............................................................................25
2.3.1 Processor Subsystem (ARM926) .............................................................................................25
2.3.1.1 Features ..............................................................................................................................26
2.3.1.2 Block diagram ......................................................................................................................26
2.3.1.3 ARM926EJ-S processor .......................................................................................................27
2.3.1.3.1 Cache structure of ARM926EJ-S ....................................................................................27
2.3.1.3.2 ARM926 Tightly Coupled Memories (ARM926_TCM) .....................................................28
2.3.1.3.3 Memory Management Unit (MMU) ..................................................................................29
2.3.1.3.4 Bus Interface of the ARM926 Processor .........................................................................30
2.3.1.3.5 ARM926 Embedded Trace Macrocell (ETM9), Trace Buffer (ETB11) ..............................30
2.3.1.4 Debug Support .....................................................................................................................31
2.3.1.4.1 Debug Configuration ......................................................................................................31
2.3.1.4.2 ARM926EJ-S Debug Interface .......................................................................................31
2.3.1.5 Boot Process for the ERTEC 200P .......................................................................................32
2.3.1.5.1 Primary Boot Loader ......................................................................................................34
2.3.1.5.2 Boot mode 1 ... 2 (booting with NOR flash) in compile mode ..........................................37
2.3.1.5.3 Boot Modes 5 and 6 (Booting with SPI Master) ...............................................................38
2.3.1.5.4 Boot Mode 7 (Booting with External Host) ......................................................................40
2.3.1.6 Secondary Boot Loader .......................................................................................................43
2.3.1.6.1 Memory Swapping by the Secondary Boot Loader..........................................................43
2.3.2 AMBA (Internal Bus System) ....................................................................................................43
2.3.2.1 Characteristics of the Bus System in ERTEC 200P ..............................................................43
2.3.2.2 Endianness ..........................................................................................................................44
2.3.2.3 AHB Subsystem (Multi-Layer AHB) ......................................................................................44
2.3.2.3.1 AHB Arbiters ..................................................................................................................45
2.3.2.3.2 AHB Multi-layer Configuration ........................................................................................45
2.3.2.3.3 AHB Burst Breaker .........................................................................................................46
2.3.2.4 APB Subsystem (Peripheral Bus) .........................................................................................47
2.3.2.4.1 APB Decoder .................................................................................................................51
2.3.2.5 Address Range and Acknowledgement Delay Monitoring .....................................................51
2.3.2.5.1 Monitoring at the AHB Side ............................................................................................51
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Technical data subject to change
6 ERTEC 200P-2 Manual
Version 1.0