Test Signal Configuration; Jtag Wiring - Siemens ERTEC 200P-2 Manual

4.4 Test Signal Configuration

Test Pins External Wiring in Function Mode
TEST low-impedance to ground (GND)
TACT low-impedance to ground (GND)
TAP_SEL low-impedance to ground (GND)
TMC1 straight to ground (GND)
TMC2 straight to ground (GND)
The module design must comply strictly with the external test signal configuration given in
the table.
For the module test, the ERTEC 200P can be switched to boundary scan mode by setting
the test signals as shown in the table below:
TACT TAP_SE
L
0 0
1 1
The boundary scan is controlled over the JTAG interface (see 3.3.8).

4.5 JTAG Wiring

The JTAG interface is an interface over which the boundary scan register can be con-
trolled or which can be used for ERTEC 200P debugging. The JTAG reset is purposefully
implemented without an internal pull resistor so that various debugger connections are
possible (Hitex or MC). A filter integrated in ERTEC 200P ensures that spikes <= 40 ns
(best case) at JTAG reset XTRST are suppressed (see 4.1.4
usually forwarded to the JTAG controller as this would require a sequence over TDI/TMS
and TCK.
The table below shows the various recommendations for external pull-up/down configura-
tions of the JTAG interface signals.
JTAG Signal ERTEC 200P
Signal Direction internal pull
(siehe Kap.
3.2 und 4.9)
XTRST in
RTCK in/out
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
TEST TMC1
0 0
0 0
Circuit for
Production
(ETB not ARM recom-
accessable
via AHB)
- 10k pulldown
- not necessary 4k7 Pulldown
480
Internal Wiring
- pull-down (ca. 50k )
- spike filter < 40 ns
- pull-down (ca. 50k )
- spike filter < 40 ns
- no pull!
- spike filter < 40 ns
- no pull!
- no spike filter!
- no pull!
- no spike filter!
TMC2
0 Function mode
0 ERTEC 200P boundary scan
mode
Circuit for recommended
Debugging, JTAG circuit
mended
(ETB
accessable
via AHB)
4k7 Pullup 10k Pulldown
default
and 4k7 Pullup
Assembly
option
4k7 Pulldown
Description
. A spike at XTRST is not
)
Recommendation from Debug
supplier (Lauterbach)
You should place a pull-down resistor
(1k - 47k) on this signal on target
side, although this is not JTAG
conform. It ensures the on-chip
debug logic is inactive when the
debugger is not connected.
If this is not required, then it can be
used to compensate the propagation
delays on driver and cable. This
allows to reach higher JTAG clock
frequencies. Therefore you need to
feed-back the TCK signal buffered or
unbuffered to this line. On an unbuff-
ERTEC 200P-2 Manual
Version 1.0