Interrupt Post-Processing - Siemens ERTEC 200P-2 Manual

or higher priority, the default vector will be entered as interrupt vector also two clocks
after the LOCKREG was written.
If interrupts have been locked using LOCKREG, they will still be entered in the Interrupt
Request register. As soon as the LOCKREG function is deactivated, these stored inter-
rupts participate again in the priority resolution and possibly initiate an interrupt.
A pending and valid interrupt leads to an active INTA output. A pending and valid fast
interrupt leads to an active INTB output.
2.3.2.10

Interrupt post-processing

The acknowledge of interrupts by the CPU is performed with a read access to the
INTAACK or INTBACK register, where the ICU returns the number of the current pending
interrupt with the highest priority. The bit with the corresponding number will be set in the
In-Service register (ISREG) and the INTA or INTB signal to the CPU is removed.
The ICU outputs a default vector when an acknowledge is performed although no inter-
rupt is present on the CPU. The null vector is used as default vector. The internal status
of the ICU with regard to IRREG and ISREG does not change.
A default vector can occur:
When the ICU receives an acknowledge command without it previously outputting
1.
a pending interrupt.
When the source of a level-triggered interrupt removes it before being confirmed by
2.
the CPU.
When an interrupt input is masked or a clear command is performed for an interrupt
3.
input while concurrently an interrupt occurs at this input. Because the CPU com-
mands arrive at the interrupt controller with a time delay, the interrupt is initially for-
warded to the CPU, however, removed after the command takes affect. If, however,
the CPU responds with acknowledge, the interrupt controller can only assign the
default vector, because in the meantime a valid interrupt is no longer present.
If the time between acknowledgment and the End of Interrupt event is less than 3
4.
ICU clock cycles, the Interrupt line to the CPU may rise again, although there is no
interrupt present. In this case the CPU will read the default vector.
Each set bit in the ISREG causes all interrupts with the same or lower priority to be disa-
bled. All occurring interrupts will be detected independent of their priority and entered in
the IRREG. Bits set in the ISREG, however, cause only interrupts with a higher priority
(higher than all interrupts represented by these bits) to output an the interrupt to the CPU.
Only when a bit in the ISREG is cleared by the EOI command will the interrupts with the
same or lower priority be reactivated.
If during the processing of an interrupt, namely between acknowledge and EOI, an inter-
rupt with higher priority occurs and also confirmed by the CPU with acknowledge, the
corresponding bit will be set in the ISREG in addition to the previously set bits.
The ICU detects the end of the interrupt processing by the EOI command that results
from any write access to INTAEND or INTBEND. Each EOI clears the bit in the ISREG
that belongs to the interrupt that currently has the highest priority.
The Interrupt Controller Unit does not require any further information from the CPU to
identify the interrupt whose bit must be cleared in the ISREG (non-specific EOI com-
mand).
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Technical data subject to change
58 ERTEC 200P-2 Manual
Version 1.0