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Register:
PRIOREG95
Bits:
6dt0
Description:
Module: /icu_ertec_addr_dec_top/icu8_inst
Register:
ID_REGISTER
Bits:
15dt0
Description:
Register:
IRVEC
Bits:
2dt0
Description:
Register:
ACK
Bits:
2dt0
Description:
Register:
IRCLVEC
Bits:
2dt0
Description:
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Reset value:
Priority Register
Specification of the priority of an interrupt request at the associated
Binary code of the priority input
Reset value:
Version number of the Interrupt Controller Unit
Version number
1: 128 IR
2: 16 IR, no ZSV error, default vector FFFFFFFFF
3: 32 IR
4: 32 IR, DBG-ACK mask
5: generic ICU
6:ICU core IP
Reset value:
Interrupt Vector Register
Number of the highest priority pending Interrupt Request
For pending valid interrupt: binary code of the Interrupt number.
Default vector: 0h
Important: If SW acknowledges the current pending Interrupt Request with
a write access on ACK, the content on IRVEC is also lost.
Reset value:
Interrupt Vector Register with IRQ Acknowledge
Acknowledge the highest priority pending interrupt request by reading the
associated interrupt vector
For valid request: binary code of the input number
Otherwise: Default vector 0h
Reset value:
Interrupt Request Clear Vector
Direct clearing of an interrupt request in the Interrupt Request Register
Binary code of the input number of the request to be cleared
5Fh
0006h
0h
0h
0h
97
Address:
617Ch
Attributes:
r
Address:
8000h
Attributes:
r
Address:
8004h
Attributes:
rh
Address:
8008h
Attributes:
rht
Address:
800Ch
Attributes:
ERTEC 200P-2 Manual
Version 1.0
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wt
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