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ERTEC 200P
XCS_SDRAM
-
XRAS_SDRAM
-
XCAS_SDRAM
-
XWE_SDRAM
-
XAV_BF
-
XRDY_BF
-
CLK_O_BF0
-
CLK_O_BF1
-
CLK_O_BF2
-
CLK_I_BF
-
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
3V3
Dir
Buffer
1V8
out
1V8
TWC1BC18ALV04SZ
out
1V8
TWC1BC18ALV04SZ
out
1V8
TWC1BC18ALV04SZ
out
1V8
TWC1BC18ALV04SZ
bidi 1V8
TWC1BC18ALV04SZ
in
1V8
TWC1IC18AS
out
1V8
TWC1BC18ALV04SZ
out
1V8
TWC1BC18ALV04SZ
out
1V8
TWC1BC18ALV04SZ
in
1V8
TWC1IC18AS
434
DS
CL
int.
fout
(mA
(pF
Pul
(MHz
)
)
l
)
bid
*)
i
G9
42
-
5
bid
*)
i
G9
42
-
5
bid
*)
i
G9
42
-
5
bid
*)
i
G9
42
-
5
*
bid
G11
)
i
42
UP
5
-
-
UP
-
*
bid
G10
)
i
42
-
125
*
bid
G10
)
i
42
-
125
*
bid
G10
)
i
42
-
125
bid
i
-
-
-
-
ERTEC 200P-2 Manual
Version 1.0
Description
used!
0.1
-
Chip select for SDRAM
0.1
-
Row address strobe
0.1
-
Column address strobe
0.1
-
Write enable for SDRAM
Address Valid BurstFlash
0.1
-
Boot(4)
Ready BurstFlash
EXT_DRIVER_DISABLE
-
-
_CS0
1
-
Feedback clock output
clock for the BurstFlash
1
-
device
clock for the BurstFlash
1
-
device
Feedback clock for syn-
chronization of read data.
MUST be connected,
-
-
even if BurstFlash is not
#
1
1
1
1
1
1
1
1
1
1
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