Startup/Shutdown - Siemens ERTEC 200P-2 Manual

Furthermore there is following problem: If the ICU assigns an interrupt and the software
acknowledges it followed by a "fast" EOI (fast means, that the EOI is issued 1-3 operating
clock cycles after acknowledge), the ICU outputs a new interrupt due to internal hardware
latencies. This new interrupt is deleted again after a few clock cycles. When the CPU
acknowledges this interrupt it will read the default vector. This scenario is only a perfor-
mance issue but not a functional one. Besides it is currently not known that any CPU is
as fast as to perform such a fast EOI after acknowledge.
Deletion of interrupts during the reset phase
If the ICU is in reset and there are already high levels pending at the interrupt inputs
when the ICU comes from the reset phase, these high levels are evaluated as rising edge
by the edge detection as regards the hardware and an interrupt is immediately entered in
the interrupt request register (since edge-triggering to the positive edge is set by default
during the reset). This is not a valid interrupt and has to be deleted again immediately by
the software by writing on INTA_IRCLVEC or INTB_IRCLVEC.
Procedure for locking priorities via LOCKREG
Since it takes a certain latency from the issuing of the software write to LOCKREG until
the register in the hardware is actually written on, it is reasonable to read back the
LOCKREG register again immediately. Only when the read-back value returns to the
CPU (it does not have to be checked if the register value is correct, it is just about the
waiting), can one be sure that no more interrupts are triggered which have a lower priority
than the priority which was entered in the LOCKREG register. Apart from that, there are
no other specialties to be observed for the writing on the register, it can be written on at
any time.
2.3.2.13.5

Startup/shutdown

After the reset, all interrupts are deactivated (dedicated mask bits set as well as the glob-
al mask bit, if any). The priority of each interrupt is the lowest priority which can be as-
signed. This means that for initializing the ICU, all interrupts have to be assigned an own
priority first before the mask bit is released. Before releasing the interrupts, it should also
be determined which interrupts are level/edge-triggered and stated which edge is the
active one, if necessary. If a priority locking is to be carried out, this has to be configured
correctly and activated before.
Furthermore, it has to be taken into account that INTAs as well as INTBs are edge-
triggered by default. If level-triggering is set, the interrupt has to be canceled at the
source. Otherwise, it triggers a new interrupt (INTA or INTB) at the CPU after the
acknowledgement.
The INTA applied to the INTB always has to be set to the same triggering. This is not
checked by the ICU and has to be ensured by the software. Moreover, the SW should
normally mask the INTA input in the INTA sub-block used as INTB since otherwise an
INTA as well as an INTB is signaled to the CPU upon the occurrence of the interrupt.
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