Siemens ERTEC200 Manuals

Manuals and User Guides for Siemens ERTEC200. We have 1 Siemens ERTEC200 manual available for free PDF download: Manual

Siemens ERTEC200 Manual

Siemens ERTEC200 Manual (97 pages)

Enhanced Real-Time Ethernet Controller

Brand: Siemens | Category: Controller | Size: 2.02 MB

Table of Contents

Table of Contents
5
1 Introduction

9
- Applications of the ERTEC 200
  9
- Features of the ERTEC 200
  9
- Structure of the ERTEC 200
  10
- Figure 1: ERTEC 200 Block Diagram
  10
- ERTEC 200 Package
  11
- Figure 2: ERTEC 200 Package Description
  11
- Signal Function Description
  12
  - GPIO 0 to 31 and Alternative Functions
    12
  - JTAG and Debug
    13
  - Trace Port
    13
  - Clock and Reset
    14
  - Test Pins
    14
  - EMIF (External Memory Interface)
    14
  - LBU, MII Interface or ETM Trace Interface
    16
  - Ethernet PHY1 and PHY2
    18
  - Power Supply
    19
  - Table 1: ERTEC 200 Pin Assignment and Signal Description
    19
2 ARM946E-S Processor

21
3 Bus System of the ERTEC 200

32
- Multilayer AHB" Communication Bus
  32
  - AHB Arbiter
    32
  - AHB Master-Slave Coupling
    32
  - APB I/O Bus
    32
  - Table 6: Overview of AHB Master-Slave Access
    32
4 O on APB Bus

33
- Boot Rom
  33
  - Table 7: Access Type and Data Width of the I/O
    33
  - Booting from External ROM
    34
  - Booting Via LBU
    34
  - Booting Via SPI
    34
  - Booting Via UART
    34
  - Memory Swapping
    34
  - Table 8: Selection of Download Source
    34
- General Purpose I/O (GPIO)
  35
- Timer 0/1/2
  38
  - Timer 0 and Timer 1
    38
    
    Timer 0/1 Interrupts
    39
    
    Timer 0/1 Prescaler
    39
    
    Cascading of Timers 0/1
    39
  - Timer 2
    39
  - Address Assignment of Timer Registers
    40
  - Timer Register Description
    40
  - Table 10: Overview of Timer Registers
    40
- F-Timer Function
  43
- Watchdog Timers
  45
  - Watchdog Timer 0
    45
  - Watchdog Timer 1
    45
  - Watchdog Interrupt
    45
  - Wdout0_N
    45
  - Wdout1_N
    45
  - Figure 6: Watchdog Timing
    45
  - Watchdog Registers
    46
  - Address Assignment of Watchdog Registers
    46
  - Watchdog Register Description
    46
  - Table 12: Overview of WD Registers
    46
- UART Interface
  48
- Synchronous Interface SPI
  54
- System Control Register
  58
5 General Hardware Functions

64
- Clock Generation and Clock Supply
  64
- Reset Logic of the ERTEC 200
  65
  - Poweron Reset
    65
  - Figure 10: Clock Supply of Ethernet Interface
    65
  - Hardware Reset
    66
  - Watchdog Reset
    66
  - Software Reset
    66
  - IRT Switch Reset
    66
  - Figure 11: Power-Up Phase of the PLL
    66
- Address Space and Timeout Monitoring
  67
  - AHB Bus Monitoring
    67
  - APB Bus Monitoring
    67
  - EMIF Monitoring
    67
- Configuration Options on the ERTEC 200
  67
- Table 18: Configurations for ERTEC 200
  68
6 External Memory Interface (EMIF)

69
7 Local Bus Unit (LBU)

74
8 DMA-Controller

85
- Table 30: DMA Transfer Modes
  85
9 Multiport Ethernet PHY

88
10 Memory Description

91
11 Test and Debugging

94
12 Miscellaneous

96
- 12.1 Acronyms/Glossary
  96
- 12.2 References
  97

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