Siemens Ertec 400 Manuals

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Siemens Ertec 400 Manual

Siemens Ertec 400 Manual (98 pages)

Enhanced Real-Time Ethernet Controller

Brand: Siemens | Category: Controller | Size: 0.97 MB

Table of Contents

Table of Contents
5
1 Introduction

9
- Applications of the ERTEC 400
  9
- Features of the ERTEC 400
  9
- Structure of the ERTEC 400
  10
- Figure 1: ERTEC 400 Block Diagram
  10
- ERTEC 400 Package
  11
- Figure 2: ERTEC 400 Package Description
  11
- Signal Function Description
  12
  - GPIO 0 to 31 and Alternative Functions
    12
  - JTAG and Debug
    13
  - Trace Port
    13
  - Clock and Reset
    13
  - TEST Pins
    13
  - EMIF, Boot/Config
    14
  - Pci/Lbu
    16
  - Rmii/MII
    18
  - Power Supply
    19
  - Table 1: ERTEC 400 Pin Assignment and Signal Description
    19
2 ARM946E-S Processors

21
3 Bus System of the ERTEC 400

32
- Multilayer AHB" Communication Bus
  32
  - AHB Arbiter
    32
  - AHB Master-Slave Coupling
    32
  - Table 6: Overview of AHB Master-Slave Access
    32
  - APB I/O Bus
    33
4 O on APB Bus

33
- Boot Rom
  33
- General Purpose I/O (GPIO)
  35
- Timer 0 and Timer 1
  37
  - Mode of Operation of Timers
    38
  - Timer Interrupts
    38
  - Timer Prescaler
    38
  - Cascading of Timers
    38
  - Address Assignment of Timer 0/1 Registers
    38
  - Table 10: Overview of Timer Registers
    38
  - Timer 0/1 Register Description
    39
- F - Counter
  41
- Watchdog Timers
  43
  - Watchdog Timer 0
    43
  - Watchdog Timer 1
    43
  - Watchdog Interrupt
    43
  - Wdout0_N
    43
  - Wdout1_N
    43
  - Figure 6: Watchdog Timing
    43
  - Watchdog Registers
    44
  - Address Assignment of Watchdog Registers
    44
  - Watchdog Register Description
    44
  - Table 12: Overview of WD Registers
    44
- Uart1/ Uart2
  46
- Figure 7: Block Diagram of UART
  46
- Table 13: Baud Rates for UART at F
  47
- UARTCLK =50 Mhz
  47
5 General Hardware Functions

63
- Clock Generation and Clock Supply
  63
- Reset Logic of the ERTEC 400
  65
  - Hardware Reset
    65
  - Figure 10: Clock Supply of Ethernet Interface
    65
  - Figure 11: Power-Up Phase of the PLL
    65
  - Watchdog Reset
    66
  - Software Reset
    66
  - PCI Bridge Reset
    66
  - Actions When HW Reset Is Active
    66
- Address Space and Timeout Monitoring
  67
  - AHB Bus Monitoring
    67
  - APB Bus Monitoring
    67
  - EMIF Monitoring
    67
  - PCI Slave Monitoring
    67
6 External Memory Interface (EMIF)

69
7 Local Bus Unit (LBU)

74
8 PCI Interface

83
9 Memory Description

92
10 Test and Debugging

95
- 10.1 ETM9 Embedded Trace Macrocell
  95
  - 10.1.1 Trace Modes
    95
  - 10.1.2 Features of the ETM9 Module
    95
  - 10.1.3 ETM9 Registers
    95
- 10.2 Trace Interface
  96
- 10.3 JTAG Interface
  96
- 10.4 Debugging Via UART1
  96
- Table 30: Pin Assignment of JTAG Interface
  96
11 Miscellaneous

97
- 11.1 Acronyms/Glossary
  97
- 11.2 References
  98

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