Host Interface - Parallel (Xhif); Block Diagram Of The Host Interface; Figure 19: Block Diagram Of The Host Interface - Siemens ERTEC 200P-2 Manual

2.3.6 Host Interface – Parallel (XHIF)
Parallel external host access is processed over the host interface.
A local bus unit (2x XHIF-IP) is implemented for access to a host system connected in
parallel. The local bus unit (XHIF) has two internal XHIF-IPs and supports access from an
external 16-bit and 32-bit host CPU. The complete ERTEC 200P address range can be
accessed by the external host system over the host interface (over a max. of 8 configura-
ble address windows (pages) of 256 bytes each – 1 / 2 MByte (see below)).
The host interface is configured in the "Parameter" module with APB access.. The basic
configuration (data width, ready polarity, read/write line) for the XHIF is set (jointly for the
two IP XHIF_0/XHIF_1) with a PowerOn reset over HW_ConfigPins 5...3. Subsequent
changes can be made to this configuration by the ARM926EJ-S in the XHIF_CONTROL
register over the APB interface. The external host should not access this register, as this
could cause undefined states at the host interface. The basic configuration therefore
cannot subsequently be changed by the external host.

2.3.6.1 Block Diagram of the Host Interface

Figure 19: Block diagram of the host interface

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