Emc Timing; Sram Timing; Sram Timing For Read Access - Siemens ERTEC 200P-2 Manual

3.3.1 EMC Timing

Important:
To achieve the timing below, configure EXTENDED_CONFIG.SODM = '0' (default value).
EXTENDED_CONFIG.SODM = '1' is not permitted

3.3.1.1 SRAM Timing

The use of XRDY_PER is optional and can be enabled with ASYNC_BANKx.EW. Wait-
States can be inserted if XRDY_PER is used.
For the asynchronous SRAM interface an "active interface" is selectable. Active interface
means that at the end of a transfer the data bus is actively driven high for one AHB clock
cycle. This is necessary together with the use of internal PullUps to speed up the reloading
of the wiring capacity.
After the active phase the internal PullUps are driving the data bus and there is no need
for external PullUps on the board.

3.3.1.1.1 SRAM Timing for read access

Parame- Description
ter
t Read
R_SU
Time
t Read
R_STROBE
Time
t Read Hold-Time
R_HOLD
t Data Setup Time 5.4ns
SU_DATA
t Data Hold Time
H_DATA
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Min
Setup- 0 Tc – 4.5
ns
Strobe- 1 Tc – 4.2
ns
1 Tc – 4.8
ns
2.1 ns
452
Max depends on Register
15 Tc + 4.8 ASYNC_BANKx.R_SU
ns
64 Tc + 4.4 ASYNC_BANKx.R_STR
ns OBE
8 Tc + 4.4 ASYNC_BANKx.R_HOL
ns D
Note
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ERTEC 200P-2 Manual
Version 1.0