Reset System - Siemens ERTEC 200P-2 Manual

2.3.9.4 Reset System

There are a number of options for asynchronous ERTEC 200P resets alongside an exter-
nal PowerOn reset (XRESET): an additional external hardware reset by the debugger
(XSRST), an internal ARM926 watchdog reset (XRES_ARM926_WD) and a number of
resets with the software. The reset matrix shows all reset sources (rows) and their implica-
tions for each circuit component (columns).
A PowerOn reset (XRESET) is applied to ERTEC 200P with an external pin. This
PowerOn reset resets the entire circuit (incl. clock system). The XSRST pin is used for a
hardware reset by the debugger. The clock system is not reset and communication over
the JTAF interface is possible during this reset phase. The ERTEC 200P can be monitored
with an ARM926 watchdog. An ARM926 watchdog event (XRES_ARM926_WD) then
resets the ERTEC 200P. The SCRB register 'ASYN_RES_CTRL_REG' (see 2.3.10.9.22 )
X
allows you to exclude the PN-IP from a watchdog reset (EN_WD_RES_PN).
'ASYN_RES_CTRL_REG' can also be used by the software to trigger an internal asyn-
chronous reset without the PN-IP (RES_SOFT), an internal asynchronous reset for the
PN-IP (RES_SOFT_PN) only, an internal asynchronous reset for the ARM926 core system
(RES_SOFT_ARM926_CORE). The trigger event for the last reset for the ARM926EJ-S
core can be read from the SCRB register RES_STAT_REG (see 2.3.10.9.22 ).
X
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