Siemens ERTEC 200P-2 Manual page 11

Enhanced real-time ethernet controller
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4.6
PHY Wiring ..................................................................................................................................481
4.6.1
PHY-TX Wiring ......................................................................................................................481
4.6.1.1
PHY-TX Wiring - not used .................................................................................................482
4.6.2
PHY-FX Wiring ......................................................................................................................483
4.6.2.1
PHY-FX Wiring - not used .................................................................................................485
4.6.2.2
PHY-SD Wiring - Avago QFBR-5978AZ ............................................................................485
4.6.2.2.1 PxSD circuit .................................................................................................................485
4.6.2.2.2 GPIO circuit .................................................................................................................485
4.7
Wiring of pins not used ...............................................................................................................486
4.8
Operating Conditions ..................................................................................................................488
4.8.1
Power Up...............................................................................................................................488
4.8.2
Wiring of CTRL-STBY ............................................................................................................488
4.8.3
Power-Up Sequence (PLL) ....................................................................................................489
4.8.4
PLL Behavior .........................................................................................................................489
4.8.4.1
following crystal break ........................................................................................................489
4.8.4.2
upon temporary clock failure ..............................................................................................489
4.8.5
Readiness of internal resources once a reset is cleared .........................................................490
4.9
Pull-up/Pull-down Resistor Values .............................................................................................490
4.10
Schmitt Trigger Characteristics ..................................................................................................490
4.11
Module and ASIC Code (Chip ID) ................................................................................................490
4.12
Power dissipation ........................................................................................................................491
5
PACKAGE ................................................................................................................ 493
5.1
Package Drawing .........................................................................................................................493
5.2
Ball Layout ...................................................................................................................................493
5.3
Marking (Printed) .........................................................................................................................495
5.3.1
Order codes ...........................................................................................................................495
5.4
SiP - FPBGA400 Thermal Characteristics .................................................................................495
5.4.1
5.5
Solder Profile ...............................................................................................................................497
5.6
Packing Information ....................................................................................................................498
5.6.1
Tray .......................................................................................................................................498
5.6.2
6
QUALITY .................................................................................................................. 499
6.1
Hard-Error FIT rates ....................................................................................................................499
6.2
Soft-Error FIT rates......................................................................................................................499
7
MISCELLANEOUS ................................................................................................... 500
7.1
Abbreviations ..............................................................................................................................500
7.2
Literature list ...............................................................................................................................501
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
.................................................................................................496
J
11
ERTEC 200P-2 Manual
Version 1.0

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