Phy-Fx Wiring - Not Used; Phy-Sd Wiring - Avago Qfbr-5978Az; Pxsd Circuit; Gpio Circuit - Siemens ERTEC 200P-2 Manual

Enhanced real-time ethernet controller
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4.6.2.1 PHY-FX Wiring – not used
PxTDXP/N Signals on unused FX port should be left open, PxRDXP/N and PxSDXP/N
inputs should directly connected to GND, the GPIOs could used for alternate function.
4.6.2.2 PHY-SD Wiring – Avago QFBR-5978AZ
The Avago QFBR-5978AZ has a single ended output and ERTEC 200P has a differential
LVPECL input.

4.6.2.2.1 PxSD circuit

The following level translation circuit is recommended by direct connecting of PxSD
signals. Comparator should be placed near transceiver and PECL driver near ERTEC
200P. The 3,3V supply voltage tolerance for POF transceiver and SD level translation
circuit is limited to +- 5%.

4.6.2.2.2 GPIO circuit

Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
PxTDXP
open
PxTDXN
open
PxRDXP
PxRDXN
PxSDXP
PxSDXN
GND
GPIO(4) / GPIO(6)
Alternate function
GPIO(5) / GPIO(7)
Alternate function
PxFXEN
open

Figure 56: FX circuit unused pins

SD level translation circuit
485
ERTEC 200P-2 Manual
Version 1.0

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