Siemens ERTEC 200P-2 Manual page 178

28 TM4
29 TM2
30 TM1
31 reserved_5
Register: AT_ADDR
Bits: 31dt0
Description:
Register: LPEMR
Bits: 31dt0
Description:
Bit Identifier
12dt0 LPEMR
31dt13 reserved_1
Register: BF_CONFIG
Bits: 31dt0
Description:
Bit Identifier
0 BF_CLK_F
1 BF_CLK_EN
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Technical data subject to change
0h r
0h r
0h r
0h r
Reset value:
Async. Timeout Address register
Contains after asyc. timeout address of the access, which was finished
with timeout.
Reset value:
Low Power Extended Mode Register
This value is written into Extended Mode Register of Mobile SDRAM
Reset Attr.
0000h r
00000h r
Reset value:
Burstflash ROM Configuration register
Reset Attr.
0h r
0h r
Test Mode bit 4
0 = normal operation
w
1 = async write data outputs toggle 1 clock
after address outputs
Test Mode bit 2
0 = normal operation
w
1 = all SDRAM reads/writes are of type miss
(32 bit SDRAM only)
Test Mode bit 1
0 = normal operation
w
1 = SDRAM initialization delay after reset is
cleared
w reserved
00000000h
00000000h
Function / Description
This value is written into Extended Mode
w Register of Mobile SDRAM.
See Mobile SDRAM datasheet.
reserved
00000000h
Function / Description
Clock Frequency
0 = Burstflash clock = HCLK/2
1 = Burstflash clock = HCLK
(HCLK = AHB clock)
Clock Enable
178
Address: 24h
Attributes: rh
Address: 28h
Attributes: r (w)
Address: 2Ch
Attributes: r (w)
ERTEC 200P-2 Manual
Version 1.0