Bus System Of The Ertec 400; Multilayer Ahb" Communication Bus; Ahb Arbiter; Ahb Master-Slave Coupling - Siemens Ertec 400 Manual

3

Bus System of the ERTEC 400

The ERTEC 400 has two different buses internally.
High-performance communication bus (multilayer AHB bus)
I/O bus (APB bus)
The following function blocks are connected directly to the multilayer AHB bus:
ARM946E-S
IRT switch
LBU
PCI
Interrupt controller
Local SRAM
EMIF interface
The master can access the remaining I/O connected to the low-performance APB bus via an AHB/APB bridge. Of
the PCI and LBU masters, only one can be active. The selection is made using the CONFIG[2] input pin.
3.1

"Multilayer AHB" Communication Bus

The multilayer AHB bus is characterized by a high bus availability and data transmission. The multilayer AHB bus
is a 32-bit wide bus with multiple master capability. It runs at a frequency of 50 MHz and has the functionality of
the ARM AHB bus (see Section 3 of document /4/). Through interconnection of multiple AHB segments in the
multilayer AHB bus, three masters can access various slaves simultaneously. Of the PCI bridge and LBU
masters, only one is active at a time. The active node is set by the CONFIG[2] hardware pin during the reset
phase.
3.1.1

AHB Arbiter

Arbiters control the access when multiple masters access a slave simultaneously. Each of
the AHB arbiters uses the same arbitration procedure. "Round robin" is specified. Alternatively, a fixed priority
assignment of the AHB master can be set through assignment of the ARB_MODE bit in the M_LOCK_CNTL
system control register. Fixed priority assignment should be avoided due to the dynamic sequences on the
multilayer AHB bus. The round robin arbitration procedure prevents mutual blocking of the AHB master over a
long period on the multilayer AHB bus.
If the priority assignment is fixed, the ARM has the highest priority, followed by IRT and finally, PCI/LBU.
3.1.2

AHB Master-Slave Coupling

Not every AHB master is connected to each AHB slave. The table below shows which AHB masters can
communicate with which AHB slaves.
Slave
APB
Slave 1
Master
ARM X
IRT
PCI/LBU X

Table 6: Overview of AHB Master-Slave Access

For closed-loop control applications, attention must be paid that AHB masters do not block each other over a long
period. This would be possible if, for example, a PCI master and ARM master want to access the same IRT slave
with a time lag. In this case, the ARM master would have to pause in a "Wait" until the PCI master enables the
IRT slave again. To prevent this situation, monitoring is integrated into the PCI/LBU AHB masters and IRT switch,
which enables the slave momentarily via an IDLE state after 8 consecutive data transfers (burst or single access).
In this phase, another AHB master can access this slave.
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
(Master/Slave)
(Master)
(Master)
(Master/Slave)
(Slave)
(Slave)
(Slave)
AHB Master-Slave Coupling
EMIF
Slave 2 Slave 3
X
X
X
PCI IRT
Slave 4
X X
X
X
Page
32
Local RAM INT Control
Slave 5 Slave 6
X X
X
X
ERTEC 400 Manual
Version 1.2.2