External Bus Clock; Example Setting In Start91460.Asm - Fujitsu MB88121 Application Note

3.1.5 External bus clock

To finalise the bus interface settings the external Bus clock needs to be setup. This clock is
output at MCLKO pin. The maximum bus clock frequency at MB88121 side is 33MHz.
Based on a 4MHz external oscillator and internal PLL circuitry the maximal core frequency of
MB91F467D (CLKB) can reach 96MHz. Accordingly the maximal external bus frequency
(CLKT) is 48MHz.
Register DIVR1 configures the clock used by the external bus interface (CLKT). The
example is using following setting:
•
CLKB = 64MHz (CPU frequency)
•
CLKT = CLKB/2 =32MHz
CLKB = [main oscillator * (PLLDIVM + 1) * ( PLLDIVN + 1 ) ] / [ (PLLDIVM + 1) * (DIVR0_B + 1) ]
= [ 4MHz * 2 * 16 ] / [ 2 * 1]
= 64 MHz

3.1.5.1 Example setting in start91460.asm

Following shows the setting required in start91460.asm file.
;==============================================
; 4.6 Clock Selection
;==============================================
; There exist 3 internal clock trees:
; CPU clock, peripheral clock and external bus clock
#set CLOCKSOURCE MAINPLLCLOCK
#set PLLx16 0x010F
#set PLLSPEED PLLx16
; PLLSPEED corresponds to the registers PLLDIVM and PLLDIVN at the
; address 0x48Ch and 0x48Dh.
#set DIV_G 0x0F
#set MUL_G 0x0F
; PLL auto gear-up and auto gear-down
; recommendation settings for 64MHz
;========================================================
; 4.6.3 Select CPU and peripheral and External-bus clock
;========================================================
#set BASECLOCK_DIV2 0x01
#set EXTBUSCLOCK BASECLOCK_DIV2
;===============================================
; 6.5.5.2 Set External Bus interface clock
;===============================================
; register DIVR1 set the clock division ratio (relative to the base
; clock) for the clock used by the external bus interface (CLKT).
; Always write 0 to the lower 4 bits of DIVR1 register
LDI #0x0487, R2
LDI #(EXTBUSCLOCK
STB R3, @R2
MCU-AN-300016-E-V10
Interfacing MB91460 TO MB88121
Chapter 3 Software
; select main clock with PLL
; CLKB = 64MHz
; register PLLDIVG at address 0x48Eh
; register PLLMULG at address 0x48Fh
; 1/2 CLKB
; external bus clock CLKT=32MHz.
; Set DIVR1
<< 4), R3 ;
- 34 - © Fujitsu Microelectronics Europe GmbH