Fpga Mezzanine (Fmc) Card Interface; Lpc Connectors J3 And J4 - Xilinx ZC702 User Manual

PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can
be High during the PS supply power ramps.
Refer to UG585, Zynq-7000 All Programmable SoC Technical Reference Manual for
information concerning the resets.

FPGA Mezzanine (FMC) Card Interface

[Figure 1-2, callout 24]
The ZC702 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by
providing subset implementations of low pin count (LPC) connectors at J3 and J4. Both
connectors use a 10 x 40 form factor that is partially populated with 160 pins. The
connectors are keyed so that a the mezzanine card faces away from the ZC702 board when
connected.
Signaling Speed Ratings:
• Single-ended: 9 GHz (18 Gb/s)
• Differential Optimal Vertical: 9 GHz (18 Gb/s)
• Differential Optimal Horizontal: 16 GHz (32 Gb/s)
• High Density Vertical: 7 GHz (15 Gb/s)
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a –3 dB insertion loss point within a two-level signaling environment.
Connector Type:
• Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
For more information about SEAF series connectors, go to the Samtec website

LPC Connectors J3 and J4

[Figure 1-2, callout 24]
The 160-pin LPC connector defined by the FMC specification
connectivity for up to:
• 68 single-ended or 34 differential user-defined signals (34 LA pairs, LA00–LA33)
• 1 GTX transceiver
• 1 GTX clock
• 2 differential clocks
• 61 ground and 10 power connections
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
www.xilinx.com
Feature Descriptions
[Ref
(Figure B-1, page 65) provides
13].
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