Fpga Mezzanine (Fmc) Card Interface; Hpc Connector J37 - Xilinx ZC706 User Manual

Depressing and then releasing pushbutton SW3 causes PS_SRST_B_SW (connected to the
XC7Z045 AP SoC U1 dedicated PS Bank 500 pin D21) to strobe low.
PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can
be High during the PS supply power ramps.
See Zynq-7000 All Programmable SoC Technical Reference Manual (UG585) for information
concerning the resets.

FPGA Mezzanine (FMC) Card Interface

[Figure 1-2, callout 30 and 31]
The ZC706 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC)
specification by providing subset implementations of the high pin count (HPC) connector at
J37 and low pin count (LPC) version at J5. Both connectors use a 10 x 40 form factor. The
HPC connector is populated with 400 pins, while the LPC connector is partially populated
with 160 pins. The connectors are keyed so that a mezzanine card, when installed in either
of these FMC connectors on the ZC706 evaluation board, faces away from the ZC706 board.
Connector Type:
• Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
More information about SEAF series connectors is available at the Samtec website
More information about the VITA 57.1 FMC specification is available at the VITA FMC
Marketing Alliance website

HPC Connector J37

[Figure 1-2, callout 30]
The 400-pin HPC connector defined by the FMC specification
provides connectivity for up to:
• 160 single-ended or 80 differential user-defined signals
• 10 GTX transceivers
• 2 GTX clocks
• 4 differential clocks
• 159 ground and 15 power connections
The connections between the HPC connector at J37 and AP SoC U1
a subset of this connectivity:
• 34 differential user-defined pairs (34 LA pairs, LA00–LA33)
ZC706 Evaluation Board User Guide
UG954 (v1.5) September 10, 2015
[Ref 37].
www.xilinx.com
Feature Descriptions
[Ref
(Figure B-2, page 91)
(Table 1-32) implements
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31].
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