Agilent Technologies 93000 SOC Series Training Manual page 25

2-2 Creating a Test Plan
CP
mode
_MR
tw_MR
ser_in
ser_out
tw_CP
ts_Sx_CP
th_CP_Sx
Agilent 93000 SOC Series User Training Part 1, October 2004
Table 4 74ACT299 Logic Table
_MR S1
0 X
1 1
1 0
1 1
1 0
Timing
tw_CP
th_CP_Sx
ts_Sx_CP
trec_MR_CP
ts_DSx_CP th_CP_DSx
tpd_CP_Qx
Clock puls width
Setup time of the pins S0 and S1
Hold time of the pins S0 and S1
Figure 5 74ACT299 Timing
S0 CP Response/Action
X X Asynchronous Reset; Q0-Q7 = LOW
1 Parallel Load; I/On => Qn
1 Shift Right; DS0 => Q0, Q0 => Q1, etc.
0 Shift Left; DS7 => Q7, Q7 => Q6, etc.
0 X Hold
ts_IOx_CP th_CP_IOx
tw_MR Width of the master reset pulse
trec_MR_CP Recovery time to the following clock pulse
ts_DSx_CP Setup time of the pins DS0 and DS7
th_CP_DSx Hold time of the pins DS0 and DS7
tpd_CP_Qx Propagation delay ofo the pins Q0 and Q7
ts_IOx_CP Setup time of the io bus
th_CP_Iox Hold time of the io bus
tpd_CP_Iox Propagation delay of the io bus
Test Engineer's Responsibilities
tw_CP
io_pins (i)
tpd_CP_IOx
io_pins (o)
CP
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