Ddr Clock Routing Guidelines; Ddr Clock Routing Topology (Sck[5:0]/Sck[5:0]#) - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
System Memory Design Guidelines (DDR-SDRAM)
Figure 64. DDR Clock Routing Topology (SCK[5:0]/SCK[5:0]#)
G M C H
G M C H
Pin
NOTE: R1 is located on the DIMM module.
5.4.3

DDR Clock Routing Guidelines

Table 30
Table 30. DDR Clock Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Differential Mode Impedance (Zdiff)
Nominal Trace Width
(See exceptions for breakout region below.)
Nominal Pair Spacing (edge to edge)
(See exceptions for breakout region below)
Minimum Pair-to-Pair Spacing
(See exceptions for breakout region below.)
Minimum Serpentine Spacing
Minimum Spacing to Other DDR Signals
(See exceptions for breakout region below.)
Minimum Isolation Spacing to Non-DDR
Signals
Maximum Via Count
NOTES:
1. Pad-to-pin length tuning is used on clocks to achieve minimal variance. Package lengths range between
approximately 600 mils and 1400 mils. Exact package lengths for each clock signal are provided at the
end of this section. Overall target length shall be established based on placement and routing flow. The
resulting motherboard segment lengths must fall within the ranges specified.
2. The DDR clocks shall be routed on internal layers, except for pin escapes. It is recommended that pin
escape vias be located directly adjacent to the ball pads on all clocks. Surface layer routing shall be
minimized.
3. Exceptions to the trace width and spacing geometries are allowed in the breakout region to fan-out the
interconnect pattern. Reduced spacing shall be avoided as much as possible.
126
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6300ESB ICH Embedded Platform Design Guide
P 1
P 1
presents the DDR clock signal group routing guidelines.
Parameter
L 1 L 2
L 2
L 1
D iffe ren tia l P a irs
SCK[5:0] and SCK[5:0]#
Differential Pair Point to Point
Ground Referenced
42 Ω ± 15%
70 Ω ± 15%
Inner Layers: 7 mils
Outer Layers: 8 mils (pin escapes only)
Inner Layers: 4 mils
Outer Layers: 5 mils (pin escapes only)
20 mils
20 mils
20 mils
25 mils
2 (per side)
D IM M P A D S
Definition
R 1