Signal Propagation Time-To-Distance Relationship And Assumptions; Recommended Stack-Up Capacitive Coupling Model - Intel 855GME Design Manual

Chipset, ich embedded platform
Hide thumbs Also See for 855GME:
Table of Contents

Advertisement

®
Intel
855GME Chipset and Intel
®
Intel
Pentium
relationship given below does not take into account the normal tolerances that are allowed for in
the recommended board stack-up's parameters. For the recommended stack-up shown in
the calculated capacitive coupling maximum value is represented by the following relationship:
(C
As shown in
by Trace 1, Trace 2, and Trace 3. Based on the capacitive coupling model shown, the
aforementioned parameters are:
C
C
When a stack-up that is employed does not adhere to the recommended stack-up, a new extraction
must be made for the stack-up using a 2D field solver program. According to the 2D field solver
results, new coupling calculations must be performed to ensure that the coupling results are less
than the aforementioned capacitive coupling maximum value of 8.15 percent. When the coupling
results are greater than the maximum value, additional system-level simulations must be performed
to avoid any signal quality issues due to crosstalk effects.
Figure 6. Recommended Stack-up Capacitive Coupling Model
Note: CS1a + CS1b = C11
4.1.1.4

Signal Propagation Time-to-Distance Relationship and Assumptions

Due to the high-frequency nature of some interfaces and signals, length matching may or may not
exist as part of the routing requirements for a given interface. In general, the tolerances that
specific signals in a bus must be routed to are stated as a length measured in mils or inches and are
specific to the recommended motherboard stack-up (refer to
matching tolerances for signals listed in this design guide may be stated as a measurement of time.
In such cases, the correlation of the period of time to an actual length value depends on board
stack-up.
Based on the recommended stack-up, the signal propagation time to distance relationship, for the
purpose of this design guide, is as follows:
Strip-line (internal layer) routing: 180 ps for 1.0 inch
®
®
M/Celeron
M Processor FSB Design and Power Delivery Guidelines
/C
) x 100 = 8.15%
MUTUAL
SELF
Figure
6, the coupling values are calculated based on a three-line model, represented
= C21 + C23
MUTUAL
= C22 (Trace 2, i.e., CS2a + CS2b)
SELF
CS1a
C21
Trace 1
CS1b
CS2a + CS2b = C22
CS3a +CS3b = C33
January 2007
®
6300ESB ICH Embedded Platform Design Guide
GND
CS2a
C23
Trace 2
CS2b
GND
Section
Figure
CS3a
11.2 Mil
Trace 3
CS3b
4.8 Mil
3.1). However, some length
2,
39

Advertisement

Table of Contents
loading

This manual is also suitable for:

6300esb

Table of Contents