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®
Intel
855GME Chipset and Intel
System Memory Design Guidelines (DDR-SDRAM)
Table 34. DDR SDQ/SDM/SDQS Package Lengths (Sheet 2 of 2)
Signal
SDQS[0]
SDQS[1]
SDQS[2]
SDQS[3]
SDQS[4]
SDQS[5]
SDQS[6]
SDQS[7]
SDQS[8]
5.4.5
Control Signals – SCKE[3:0], SCS[3:0]#
The 82855GME control signals, SCKE[3:0] and SCS[3:0]#, are clocked into the DDR SDRAM
devices using clock signals SCK[5:0]/SCK[5:0]#. The GMCH drives the control and clock signals
together, with the clocks crossing in the valid control window. The GMCH provides one chip select
(CS) and one clock enable (CKE) signal per DIMM physical device row. Two chip select and two
clock enable signals are routed to each DIMM. Refer to
DIMM mapping.
Table 35. Control Signal to DIMM Mapping
Signal
SCS[0]#
SCS[1]#
SCS[2]#
SCS[3]#
SCKE[0]
SCKE[1]
SCKE[2]
SCKE[3]
The control signal routing shall transition from an external layer to an internal signal layer under
the GMCH, keep to the same internal layer until transitioning back out to an external layer to
connect to the appropriate pad of the DIMM connector and the parallel termination resistor. When
the layout requires additional routing before the termination resistor, return to the same internal
layer and transition back out to an external layer immediately prior to parallel termination resistor.
138
®
6300ESB ICH Embedded Platform Design Guide
Pkg Length
Pin Number
(mils)
AG2
925
AH5
838
AH8
756
AE12
466
AH17
678
AE21
487
AH24
770
AH27
858
AD15
418
Relative To
DIMM0
DIMM0
DIMM1
DIMM1
DIMM0
DIMM0
DIMM1
DIMM1
Signal
Pin Number
SDQ[67]
SDQ[68]
SDQ[69]
SDQ[70]
SDQ[71]
SDM[0]
SDM[1]
SDM[2]
SDM[3]
SDM[4]
SDM[5]
SDM[6]
SDM[7]
SDM[8]
Table 35
for the CKE and CS# signal to
DIMM Pin
AD23
AD26
AC22
AC25
AC7
AB7
AC9
AC10
Pkg Length
(mils)
AG16
530
AH14
701
AE15
421
AF16
491
AF17
530
AE5
838
AE6
693
AE9
538
AH12
606
AD19
492
AD21
470
AD24
557
AH28
917
AH15
685
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