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®
Intel
855GME Chipset and Intel
Table 153.
USB 2.0 Layout Checklist (Sheet 2 of 2)
#
Minimize the length of high-speed clock and periodic signal traces
11
that run parallel to USB signal lines to minimize crosstalk. The
minimum recommended spacing to clock signals is 100 mils.
Use 45 mils minimum spacing between USB signal pairs and
12
other signal traces. This helps to prevent crosstalk.
USB signal pair traces should be trace length matched. Max trace
13
length mismatch between USB signal pair (such as DM1 and
DP1) should be no greater than 60 mils.
14
No termination resistors are needed for USB.
Short USBRBIAS and USBRBIAS# at the package, connect with
15
a 5 mils width, 5 mils spacing single trace 500 mils or less to the
22.6 Ω 1% resistor to ground.
Maximum length from the 6300ESB to the backpanel should not
16
exceed recommend length
Maximum length from the 6300ESB to the CNR should not
17
exceed recommend length
Maximum length from the 6300ESB to the Front Panel connector
18
should not exceed recommend length
13.3.5
AC'97 Layout Checklist
Table 154.
AC'97 Layout Checklist
#
1
5 mils trace width, 10 mils spacing between traces.
AC_SDIN Max Trace Length
2
6300ESB to the Primary Codec or CNR connector is 14 inches
AC_SDOUT Max trace length
3
6300ESB to the Primary Codec or CNR connector is 14 inches
AC_BIT_CLK Max trace length
4
6300ESB to the Primary Codec or CNR connector is 14 inches
Series termination resistor on AC_BIT_CLK line should be no
5
more than 3.0 to 8.0 inches from the 6300ESB.
13.3.5.1
RTC Layout Checklist
Table 155.
RTC Layout Checklist
#
1
RTC LEAD length = one inch maximum
2
Minimize capacitance between RTCX1 and RTCX2.
3
Put GND plane underneath Crystal components.
Don't route switching signals under the external components
4
(unless on other side of board).
®
6300ESB ICH Embedded Platform Design Guide
Layout Recommendations
Layout Recommendations
Layout Recommendations
January 2007
Layout Checklist
Comments
Comments
Comments
315
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