Page 1 Datasheet November 2007 ® Notice: The Intel 6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Order Number: 300641-004US...
Page 2 The Intel 6300ESB I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications.which may cause the product to deviate from published specifications. which may cause the product to deviate from published specifications.
Page 3 ® —Intel 6300ESB ICH ® Intel 6300ESB I/O Controller Hub Product Features • • 8-Bit Hub Interface Power Management Logic — 266 Mbyte/s maximum throughput — ACPI 1.0 compliant — Parallel Termination scheme for longer — ACPI-defined power states S1 (Stop...
Page 4 — Second stage drives external pin active until cleared by a system reset or power cycle — Configuration option for write-once enabling (count values can still change) — Configurable granularity from 1µs to 10 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 5: Workstation/Pc Model
Hard Disk Hard Disk / ® Intel CD-DVD PCI-X 6300ESB GBE / SCSI SATA Hard Disk Controller Legacy Peripherals SATA Hard Disk GPIO USB 2.0 AC'97 SM Bus B2475-02 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 6: Low To Mid-Range Communication Appliance Model (Diskless)
Processor System Bus Memory ® Intel HL 1.5 256 MB 875P MCH to 1GB Hublink Hard Disk ® Intel PCI-X GBE / 6300ESB 2D Graphics GPIO's Controller SM Bus B2476-02 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 7: Value Server, Ultra-Dense Server And Low-End Server Blade
1GB to 2 GB E7210 MCH Hublink 1.5 PCI-X Hard Disk ® Intel Hard Disk 6300ESB 2D Graphics SATA Controller Hard Disk USB 2.0 SATA Hard Disk SM Bus GPIO B2477-03 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 8: Table Of Contents
3.21.1 Functional Straps..................77 3.22 Revision and Device ID Table ................78 ® Intel 6300ESB ICH Power Planes and Pin States ............79 Power Planes.....................79 Integrated Pull-Ups and Pull-Downs..............80 IDE Integrated Series Termination Resistors............81 Output and I/O Signals Planes and States .............81 Power Planes for Input Signals ................83 Functional Description .....................91...
Page 9 I/O Cycles................102 5.2.1.9 Bus Master Cycles ..............102 5.2.1.10 LPC Power Management............102 ® 5.2.1.11 Configuration and Intel 6300ESB ICH Implications ....102 DMA Operation (D31:F0) .................. 103 5.3.1 DMA Overview ..................103 5.3.2 Channel Priority ................... 104 5.3.2.1 Fixed Priority ................
Page 10 5.11 Power Management (D31:F0) ................145 5.11.1 Features ....................145 ® 5.11.2 Intel 6300ESB ICH Power States and Transition Rules ......146 5.11.3 System Power Planes ................148 ® 5.11.4 Intel 6300ESB ICH Power Planes ............148 5.11.5 SMI#/SCI Generation................149 5.11.6 Dynamic Processor Clock Control ............
Page 11 5.13.3 SMI# and SCI Routing ................178 5.13.4 Triggering ................... 178 5.14 IDE Controller (D31:F1) ................... 178 5.14.1 Overview .................... 178 5.14.2 PIO Transfers ..................179 5.14.2.1 Overview ................179 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 12 5.17.3.3 Command Register, Status Register, and TD Status Bit Interaction 204 5.17.3.4 Transfer Queuing ..............204 5.17.4 Data Encoding and Bit Stuffing ............... 208 5.17.5 Bus Protocol..................208 5.17.5.1 Bit Ordering................208 5.17.5.2 SYNC Field ................208 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 13 5.19.2.3 Heartbeat for Use with the External LAN Controller ...... 249 5.19.3 Bus Arbitration..................249 5.19.4 Bus Timing ..................249 5.19.4.1 Clock Stretching ..............249 ® 5.19.4.2 Bus Time Out (Intel 6300ESB ICH as SMBus Master) ....250 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 14 Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0) ....288 7.1.3 Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)....289 7.1.4 Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—D30:F0) .. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 15 Register (HUB-PCI—D30:F0)..............304 7.1.26 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register (HUB-PCI—D30:F0) ............305 ® 7.1.27 Offset 50 - 51h: CNF—Intel 6300ESB ICH Configuration Register (HUB-PCI— D30:F0)306 7.1.28 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0) 7.1.29 Offset 70h: MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0) ................
Page 16 8.1.34 Offset EEh - EFh: FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0) ................341 8.1.35 Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—D31:F0) . 8.1.36 Offset F2h: FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) ................343 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 17 CPU Interface Registers..................381 8.7.1 NMI_SC—NMI Status and Control Register ..........381 8.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) ........382 8.7.3 PORT92—Fast A20 and Init Register ............382 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 18 8.10.1 GPIO Register I/O Address Map .............. 425 8.10.2 Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register ... 426 8.10.3 Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select Register ..426 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 19 10.1.1 Offset 00 - 01h: VID—Vendor Identification Register (USB—D29:F0/F1)................462 10.1.2 Offset 02 - 03h: DID—Device Identification Register (USB—D29:F0/F1)................462 10.1.3 Offset 04 - 05h: CMD—Command Register (USB—D29:F0/F1)................463 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 20 11.1.15Offset 51h: Next Item Pointer #1............493 11.1.16Offset 52 - 53h: Power Management Capabilities ........493 11.1.17Offset 54 - 55h: Power Management Control/Status ........494 11.1.18Offset 58h: Debug Port Capability ID............495 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 21 11.1.25 Offset 68 - 6Bh: USB EHCI Legacy Support Extended Capability ....499 11.1.26 Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status ... 500 11.1.27 Offset 70 - 73h: Intel Specific USB EHCI SMI ........... 501 11.1.28 Offset 80h: Access Control ..............503 11.1.29 HS_ Ref_V_USB HS Reference Voltage Register........
Page 22 13.1.12Offset 18 - 1Bh: MMBAR—Mixer Base Address Register (Audio—D31:F5)..557 13.1.13Offset 1C - 1Fh: MBBAR—Bus Master Base Address Register (Audio—D31:F5)..13.1.14Offset 2D - 2Ch: SVID—Subsystem Vendor ID Register (Audio—D31:F5) ..559 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 23 14.1.13 Offset 2E - 2Fh: SID—Subsystem ID (Modem—D31:F6) ......588 14.1.14 Offset 34h: CAP_PTR—Capabilities Pointer (Modem—D31:F6) ................589 14.1.15 Offset 3Ch: INTR_LN—Interrupt Line Register (Modem—D31:F6) ................589 14.1.16 Offset 3Dh: INT_PIN—Interrupt Pin (Modem—D31:F6) ......590 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 24 16.4.20Offset Base + 08h: General Interrupt Status Register ........ 628 16.4.21Offset Base + 0Ch: Reload Register............629 16.5 Theory Of Operation..................629 16.5.1 RTC Well and WDT_TOUT# Functionality..........629 16.5.2 Register Unlocking Sequence..............629 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 25 VGA Addressing ....................649 18.4 Configuration Addressing.................. 650 ® 18.4.1 Type 0 Accesses to the Intel 6300ESB ICH ..........650 18.4.2 Type 1 to Type 0 Translation..............650 18.4.3 Type 1 to Type 1 Forwarding ..............651 18.4.4 Type 1 to Special Cycle Forwarding............651 18.5...
Page 26 18.6.1.20Offset 3C: INTR—Interrupt Information ........667 18.6.1.21Offset 3E: BCTRL—Bridge Control ..........667 ® 18.6.1.22Offset 40: CNF—Intel 6300ESB I/O Controller Hub Configuration . 671 18.6.1.23Offset 42: MTT—Multi-Transaction Timer ........673 18.6.1.24Offset 44: STRP—PCI Strap Status ..........674 18.6.1.25Offset 50: PX_CAPID—PCI-X Capabilities Identifier ...... 674 18.6.1.26Offset 51: PX_NXTP—Next Item Pointer ........
Page 27 19.4.3.1 I/O Transfers ................. 707 19.5 Logical Device 4 and 5: Serial Ports (UARTs) ............707 19.5.1 Overview .................... 707 19.5.1.1 UART Feature List ..............708 19.5.1.2 UART Operational Description ........... 709 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 28 20.1.15Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)....... 747 20.1.16Offset 34h: CAP—Capabilities Pointer Register (SATA–D31:F2) ..................747 20.1.17Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2) ..................747 20.1.18Offset 3Dh: INTR_PN—Interrupt Pin Register (SATA–D31:F2) ..................748 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 29 22.5.3 IDE and Ultra ATA Timing ..............817 22.5.4 USB....................820 22.5.5 SMBus ....................821 22.5.6 Power and Reset .................. 822 22.5.7 AC’97 and Miscellaneous ............... 824 Testability ......................825 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 30 Intel 6300ESB ICH—Contents 23.1 Test Mode Description ..................825 23.2 Tri-State Mode ....................826 23.3 XOR Chain Mode....................826 23.3.1 XOR Chain Testability Algorithm Example..........826 Index ........................835 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 31 ® Intel 6300ESB ICH-USB Port Connections..............230 ® Intel 6300ESB ICH Based AC’97 Controller Connection to Companion Codec(s) .... 260 AC’97 2.2 Controller-Codec Connection ..............261 AC-Link Protocol ....................262 AC-Link Powerdown Timing ..................270 SDIN Wake Signaling....................271 ®...
Page 32 S0 to S5 to S0 Timings.................... 824 AC’97 Data Input and Output Timings ............... 824 Test Mode Entry (XOR Chain Example) ..............826 Example XOR Chain Circuitry ................... 826 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 33 Revision and Device ID Table..................78 ® Intel 6300ESB I/O Controller Hub Power Planes ............79 Integrated Pull-Up and Pull-Down Resistors ..............80 IDE Series Termination Resistors................81 Power Plane and States for Output and I/O Signal for Desktop Configurations ....83 Power Plane for Input Signals for Desktop Configurations ..........
Page 34 Configuration Bits Reset By RTCRST# Assertion............140 INIT# Going Active ....................141 NMI Sources ......................143 DP Signal Differences ....................143 ® General Power States for Systems Using Intel 6300ESB ICH ........146 ® State Transition Rules for Intel 6300ESB I/O Controller Hub........147 System Power Plane ....................
Page 35 141 AC-link State during PXPCIRST# ................273 142 PCI Devices and Functions..................276 ® 143 Fixed I/O Ranges Decoded by Intel 6300ESB I/O Controller Hub ........ 278 144 Variable I/O Decode Ranges ..................281 145 Memory Decode Ranges from CPU Perspective ............283 PCI Configuration Registers (D30:F0) ...............
Page 36 Offset 40 - 43h: HI_CMD—Hub Interface Command Control Register (HUB-PCI—D30:F0). 304 Offset 44 - 45h: DEVICE_HIDE—Secondary PCI Device Hiding Register (HUB-PCI—D30:F0) Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register (HUB-PCI—D30:F0) ... 306 174 Offset 58 - 5Bh: D30_PNE — PERR#_NMI_ENABLE Register (HUB-PCI—D30:F0)..... 307 Offset 70h: MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)
Page 37 267 NMI_EN—NMI Enable (and Real Time Clock Index) ............. 382 268 PORT92—Fast A20 and Init Register ................. 382 269 COPROC_ERR—Coprocessor Error Register ..............383 270 RST_CNT—Reset Control Register ................383 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 38 321 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2 Register ....432 322 PCI Configuration Map (IDE-D31:F1)................. 435 323 Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) ........436 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 39 371 Offset 00 - 01h: USBCMD—USB Command Register ............ 474 372 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation ....477 373 Offset 02 - 03h: USBSTA—USB Status Register ............478 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 40 ........499 Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status ......500 405 Offset 70 - 73h: Intel Specific USB EHCI SMI ............. 501 406 Offset 80h: Access Control..................503 HS_ Ref_V_USB HS Reference Voltage Register ............503 408 Offset 00h: CAPLENGTH—Capability Registers Length..........
Page 41 478 Offset 40h: PCID—Programmable Codec ID Register (Audio—D31:F5)......561 479 Offset 41h: CFG—Configuration Register (Audio—D31:F5) ........... 562 480 Offset 50h: PID—PCI Power Management Capability ID Register (Audio—D31:F5)... 562 481 Offset 52h: PC—Power Management Capabilities Register (Audio—D31:F5)....563 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 42 482 Offset 54h: PCS—Power Management Control and Status Register (Audio—D31:F5) ..563 ® 483 Intel 6300ESB I/O Controller Hub Audio Mixer Register Configuration ......565 484 Native Audio Bus Master Control Registers ..............566 485 x_BDBAR—Buffer Descriptor Base Address Register ............ 568 486 x_CIV—Current Index Value Register ................
Page 43 588 Offset 08: RID—Revision ID ..................658 589 Offset 09: CC—Class Code ..................659 590 Offset 0C: CLS—Cache Line Size ................659 591 Offset 0D: PLT—Primary Latency Timer ..............660 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 44 612 Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control ........678 613 Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control ....... 679 614 Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration........680 615 Offset E4: PCR - PCI Compensation Register .............. 681 616 Offset F0: HCCR - Hub Interface Command/Control Register ........
Page 45 694 Offset A4h - A7h: SRD—SATA Registers Data (SATA–D31:F2) ........761 695 STTT—SATA TX Termination Test Register A (SATA–D31:F2) ........762 696 STOT — SATA TX Output Test Register (SATA–D31:F2) ..........762 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 46 PWROK active)....................831 738 XOR Chain #6 (RTCRST# asserted for 52 PCI clocks while PWROK active)...... 834 739 XOR Chain #7 (RTCRST# asserted for 60 PCI clocks while PWROK active)...... 834 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 47: Revision History
HyperThreading Technology. — Table 191: Remove incorrect references to TCO in Note — Section 5.7.1: Removed references to three wire APIC bus. 6300ESB does not support this feature. — Table 31: Moved Note 1 refernces from I/O to Memory cycles —...
Page 48 A change bar to left of text, a table row or a figure heading indicates this item is either new or modified from the previous version of the document. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 49: Industry Specifications
About This Document This datasheet is intended for Original Equipment Manufacturers (OEMs) and BIOS ® vendors creating products based on the Intel 6300ESB I/O Controller Hub (ICH). This manual assumes a working knowledge of the vocabulary and principles of USB, IDE, AC’97, SMBus, PCI, ACPI, and LPC.
Page 50 D31:F5, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus ® number will not be used, and may be considered to be Bus 0. Note that the Intel 6300ESB ICH’s external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration.
Page 51 Chapter 22, “Electrical Characteristics” provides AC and DC characteristics and AC timings. Chapter 23, “Testability” provides information on test modes and scan chains. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 52 ® Intel 6300ESB ICH—1 This page intentionally left blank. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 53: Intel ® 6300Esb Ich And System Clock Domains
An option will be to use the 48.0 MHz clock. ® Main Clock 1.5 GHz clock generated internal to the Intel SATA 100 MHz Generator 6300ESB ICH for use by SATA phy. ®...
Page 54: Conceptual System Clock Diagram
33 MHz Clock 14.31818 MHz Gen. 48 MHz 14.31818 MHz ® Intel 6300ESB 100 MHz Diff. Pair 48 MHz 12.288 MHz AC’97 Codec(s) 32 kHz SUSCLK# (32 kHz) XTAL ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 55: Hub Interface Signals
HICOMP ® NOTE: The Intel 6300ESB ICH will only support RCOMP, not the ZCOMP mode. Hub Interface Clock: 66 MHz clock input for Hub Interface. It is also HICLK used for some other internal units. This clock will stop during S3-S5 states.
Page 56: Firmware Hub Interface Signals
Firmware Hub Signals. Muxed with LPC LFRAME# signal. LFRAME#: LFRAME# Indicates the start of an LPC cycle, or an abort. NOTE: All LPC/FWH signals are in the core well. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 57: Pci Interface Signals
As an output, the Intel 6300ESB ICH asserts DEVSEL# ® when a PCI master peripheral attempts an access to an internal Intel 6300ESB ICH address or an address destined for Hub Interface (main DEVSEL# memory or AGP). As an input, DEVSEL# indicates the response to an ®...
Page 58 ® The Intel 6300ESB ICH checks parity on the data phase when it is the Initiator of PCI read transactions and when it is the Target of PCI write transactions. It also checks parity on the address phase when it is the ®...
Page 59 Upon sampling SERR# active, the ® SERR# I/OD Intel 6300ESB ICH can be programmed to generate an NMI or SMI#. ® Implemented as I/O open drain. This allows the Intel 6300ESB ICH to drive these signals due to internal sources.
Page 60: Pci-X Interface Signals
1 1 1 1 Memory Write and Invalidate ® All command encodings not shown are reserved. The Intel 6300ESB ICH does not decode reserved values, and therefore will not respond when a PCI-X master generates a cycle using one of the reserved values.
Page 61 6300ESB ICH PXIRDY# has valid data present on PXAD[31:0]. During a read, it indicates the ® Intel 6300ESB ICH is prepared to latch data. PXIRDY# is an input to ® ® the Intel 6300ESB ICH when the Intel 6300ESB ICH is the Target ®...
Page 62 ® PCI/PCI-X Reset: The Intel 6300ESB ICH asserts PXPCIRST# to ® reset devices that reside on the PCI-X bus. The Intel 6300ESB ICH asserts PXPCIRST# during power-up and when S/W initiates a hard ® reset sequence through the RC (CF9h) register. The Intel...
Page 63 It has the same timing as PXFRAME#. When the Intel ® 6300ESB ICH is the initiator, this signal is an output. When the Intel 6300ESB ICH is the target this signal is an input PCI-X interface acknowledge 64-bit transfer: This is asserted by...
Page 64: Sata Interface Signals
1. The IDE signals are 5V tolerant. 2. The IDE signals have integrated series terminating resistors. 3. All signals may be tri-stated or driven low for mobile swap bays. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 65 DMA): This is the command to the IDE device that it may drive data ® onto the PDD or SDD lines. Data is latched by the Intel 6300ESB ICH on the deassertion edge of PDIOR# or SDIOR#. The IDE device is...
Page 66: Lpc Interface Signals
PIRQ[B]# IRQ17 PIRQ[C]# IRQ18 PIRQ[D]# IRQ19 This frees the legacy interrupts. These signals are 5V tolerant. NOTE: The Interrupt signals are 5V tolerant except for PXIRQ [3:0]# / GPIO[36:33] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 67: Usb Interface Signals
Address/Command Bus. USBP1N, NOTE: No external resistors are required on these signals. The ® USBP2P, Intel 6300ESB ICH integrates 15 kΩ pull-downs and USBP2N, provides an output driver impedance of 45 Ω which USBP3P, requires no external series resistor USBP3N...
Page 68: Power Management Interface Signals
S5 (Soft Off) state. ® Power OK: When asserted, PWROK is an indication to the Intel 6300ESB ICH that core power and PCICLK have been stable for at least 1 ms. PWROK may be driven asynchronously. When PWROK is ®...
Page 69: Cpu Interface Signals
Numeric Coprocessor Error: This signal is tied to the coprocessor ® error signal on the processor. FERR# is only used when the Intel 6300ESB ICH coprocessor error reporting function is enabled in the General Control Register (D31:F0:Offset D0.bit 5). When FERR# is ®...
Page 70 INIT# to the processor. This saves the external OR gate with ® ® the Intel 6300ESB ICH’s other sources of INIT#. When the Intel 6300ESB ICH detects the assertion of this signal, INIT# is generated RCIN# for 16 PCI clocks. ® Note that the Intel 6300ESB ICH will ignore RCIN# assertion during transitions to the S1, S3, S4 and S5 states.
Page 71: Sm Bus Interface Signals
Bias Voltage for Oscillator: Sets the proper biasing for the oscillator. Vbias Expected voltage 200 mV. NOTE: An external Crystal/Resistor/Capacitor circuit is required for proper operation of the oscillator. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 72: Other Clocks
RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). NOTES: ® 1. Clearing CMOS in an Intel 6300ESB ICH-based platform may be RTCRST# done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
Page 73: Ac'97 Link Signals
CLEAR TO SEND: Active low, this pin indicates that data may be ® exchanged between the Intel 6300ESB ICH and external interface. These pins have no effect on the transmitter. NOTE: These pins could be used as Modem Status Input whose...
Page 74: General Purpose I/O
Description DATA SET READY for UART 0, 1: Active low, this pin indicates that ® the external agent is ready to communicate with the Intel 6300ESB ICH UARTS. These pins have no effect on the transmitter. NOTE: These pins could be used as Modem Status Input whose...
Page 75: General Purpose I/O Signals
3. Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43]. 4. Resume-well GPIO are not 5 V tolerant. 5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 76: Power And Ground Signals
VCCRTC NOTE: Implementations should not attempt to clear CMOS by using a ® jumper to pull VccRTC low. Clearing CMOS in an Intel 6300ESB ICH-based platform may be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
Page 77: Functional Strap Definitions
PCI clocks prior to the time it is sampled. ® Note: The Intel 6300ESB ICH changes the polarity of the “no reboot” strap in order to avoid an audible click due to the pull-up on the SPKR output. Table 23. Functional Strap Definitions...
Page 78: Revision And Device Id Table
SATA and RAID D31:F2 RAID Controller 25B0h are mutually exclusive. NOTE: Refer to the latest Intel® 6300ESB I/O Controller Hub Specification Update for the value of the Revision Identification Registers. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 79: Intel ® 6300Esb I/O Controller Hub Power Planes
6300ESB ICH Power Planes and Pin States Power Planes ® Table 25. Intel 6300ESB I/O Controller Hub Power Planes Plane Description Main I/O Vcc3_3: Powered by the main power supply. When the system is in the S3, (3.3 V) S4, S5, or G3 state, this plane is assumed to be shut off.
Page 80: Power Plane Usage Model
7. Simulation data shows that these resistor values may range from 14.25 KΩ to 24.8 KΩ 8. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 81: Ide Series Termination Resistors
Tri-state. The Intel 6300ESB ICH is not driving the signal high or low. ® “High” The Intel 6300ESB ICH is driving the signal to a logic ‘1’. ® “Low” The Intel 6300ESB ICH is driving the signal to a logic ‘0’. “Defined”...
Page 82 ® Intel 6300ESB ICH—4 ® “Off” The power plane is off, so the Intel 6300ESB ICH is not driving. Note: The signal levels are the same in S4 and S5. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 83: Power Plane And States For Output And I/O Signal For Desktop Configurations
® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 84 ® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 85 ® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 86 ® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 87 ® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 88 ® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 89: Uart_Clk
® 1. The Intel 6300ESB ICH sets these signals at reset for CPU frequency strap. 2. The states of main I/O signals are taken at the times during PXPCIRST# and immediately after PXPCIRST#. 3. The states of resume I/O signals are taken at the times during RSMRST# and immediately after RSMRST# 4.
Page 90: Power Plane For Input Signals For Desktop Configurations
Driven SYS_RESET# Resume I/O External Circuit Driven Driven Driven THRM# Main I/O Thermal Sensor Driven THRMTRIP# CPU I/O Thermal Sensor Driven USBRBIAS# Resume I/O External Pull-Down Driven Driven Driven ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 91: Functional Description
6300ESB ICH PCI interface provides a 33 MHz, PCI Local Bus Specification, ® Rev. 2.2-compliant implementation. All PCI signals are 5 V tolerant. The Intel 6300ESB ICH integrates a PCI arbiter that supports up to four external PCI bus masters ® in addition to the internal Intel 6300ESB ICH requests.
Page 92: Intel Intel ® ® 6300Esb Ich-Usb Port Connections
5.1.3 IDSEL to Device Number Mapping ® When addressing devices on the external PCI bus (with the PCI slots) the Intel 6300ESB ICH will assert one address signal as an IDSEL. When accessing device 0, the ® ® Intel 6300ESB ICH will assert AD16. When accessing Device 1, the Intel 6300ESB ICH will assert AD17.
Page 93: Primary Device Status Register Error Reporting Logic
SSE for PCI-X (D28:06h.14) DTT_EN D28: (3Eh.11) DTSE PX PARITY ERROR (D28:04h.8) D28: 3Eh.0 PX_SERR#_ENABLE HL Parity Error D28: 04h.6 Master Abort Mode (D28.3Eh.5) HL-to-PCI-X Posted Write Master Aborts ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 94: Secondary Status Register Error Reporting Logic
SERR# Enable (D31:F0.04h.8) South PCI Delayed Transaction Timeout SERR_DTT_EN (D31:88h.1) ERROR from XL-Unit IOCHK# via SERIRQ Receive DO_SERR message from HL MCHSERR_STS (TCOBASE+04h.bit 12) SERR_RTA_EN (D31:88h.2) Received Target Abort ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 95: Nmi# Generation Logic
6300ESB ICH may detect and report different parity errors in the system. ® The Intel 6300ESB ICH may be programmed to cause an NMI (or SMI# when NMI is routed to SMI#) based on detecting a parity error. The conceptual logic diagram in ®...
Page 96: Type 0 Configuration Cycle Device Number Translation
When the Type 0 cycle on Hub Interface specifies any device number other than 29, 30 ® or 31, the Intel 6300ESB ICH will not set any address bits in the range AD[31:11] during the corresponding transaction on PCI. Table 30 shows the device number translation.
Page 97: Pci Dual Address Cycle (Dac) Support
® The Intel 6300ESB ICH supports DAC format on PCI for cycles from PCI initiators to main memory. This allows PCI masters to generate an address up to 44 bits. The size of the actual supported memory space will be determined by the Memory Controller and the processor.
Page 98: Lpc Cycle Types Supported
May be 1, 2, or 4 bytes. NOTES: ® 1. For memory cycles below 16M which do not target enabled FWH ranges, the Intel 6300ESB ICH will perform standard LPC memory cycles. It will only attempt 8-bit transfers. When the cycle appears on PCI as a 16-bit transfer, it will appear as two consecutive 8-bit transfers on LPC.
Page 99: Cycle Type Bit Definitions
Cycle Type/Direction (CYCTYPE + DIR) ® The Intel 6300ESB ICH will always drive bit 0 of this field to zero. Peripherals running bus master cycles must also drive bit 0 to 0. The following table shows the valid bit encodings: Table 33.
Page 100: Response To Sync Failures
® When the Intel 6300ESB ICH is reading data from a peripheral, data will still be transferred in the next two nibbles. This data may be invalid, but it must be transferred ®...
Page 101: Typical Timing For Lframe
6300ESB ICH will perform an abort for the following cases (possible failure cases): • ® Intel 6300ESB ICH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks. • ® Intel 6300ESB ICH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
Page 102: Lpc Power Management
Note: When the cycle is not claimed by any peripheral (and subsequently aborted), the Intel 6300ESB ICH will return a value of all ones (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high when no device responds.
Page 103: Dma Operation (D31:F0)
Bus Master Device Mapping and START Fields ® Bus Masters must have a unique START field. In the case of the Intel 6300ESB ICH, which supports two LPC bus masters, it will drive 0010 for the START field for grants to bus master #0 (requested through LDRQ[0]#) and 0011 for grants to bus master #1 (requested through LDRQ[1]#.).
Page 104: Fixed Priority
03FFFEh, not 02FFFEh. This is compatible with the 8237 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 105: Dma Transfer Size
® The Intel 6300ESB ICH maintains compatibility with the implementation of the DMA in the PC-AT which used the 8237. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note that the least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
Page 106: Software Commands
LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). ® The Intel 6300ESB ICH has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering. ® Intel...
Page 107: Dma Request Assertion Through Ldrq
® was seen by the Intel 6300ESB ICH, there is no ensuring that the cycle has not been granted and will shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may still occur. The peripheral may choose not to respond to this cycle, in which case the host will abort it, or it may choose to complete the cycle normally with any random data.
Page 108: General Flow Of Dma Transfers
® — The Intel 6300ESB ICH drives the first 8 bits of data and turns the bus around. — The peripheral acknowledges the data with a valid SYNC. — When a 16 bit transfer, the process is repeated for the next 8 bits.
Page 109: Sync Field/Ldrq# Rules
The peripheral must not assume that the next START indication from the Intel 6300ESB ICH is another grant to the peripheral when it had indicated a SYNC value of ‘1001b’. On a single mode DMA device, the 8237 will rearbitrate after every transfer.
Page 110: Timers (D31:F0)
® The Intel 6300ESB ICH contains three counters which have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. The 14.31818 MHz clock will stop during the S3-S5 and G3 states.
Page 111: Counter Operating Modes
It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 112 When a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch command is ignored. The count read will be the count at the time the first Counter Latch command was issued. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 113: Interrupt Controller Core Connections
8259 Interrupt Controllers (PIC) (D31:F0) ® The Intel 6300ESB ICH incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels.
Page 114: Interrupt Status Registers
Secondary IDE Cable mode only) or via SERIRQ, PIRQx ® The Intel 6300ESB ICH cascades the slave controller onto the master controller through master controller interrupt input two. This means there are only 15 possible ® interrupts for the Intel 6300ESB ICH PIC.
Page 115: Content Of Interrupt Vector Byte
This command is broadcast over PCI by the Intel 6300ESB ICH. ® 4. Upon observing its own interrupt acknowledge cycle on PCI, the Intel 6300ESB ICH converts it into the two cycles that the internal 8259 pair may respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers.
Page 116: Icw3
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is ® interpreted as a write to ICW1. Upon sensing this write, the Intel 6300ESB ICH PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence.
Page 117: Modes Of Operation
The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO-L2 is the binary priority level code of the bottom priority device. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 118: Poll Mode
The master controls the slaves through a three bit internal bus. In the ® Intel 6300ESB ICH, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. An EOI command must be issued twice: once for the master and once for the slave.
Page 119: Normal End Of Interrupt
® The Intel 6300ESB ICH may be programmed to allow PIRQA#-PIRQH# to be internally routed to interrupts 3-7, 9-12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers, located at 60-63h and 68-6Bh in function 0.
Page 120: Port 60 Read Clearing Irq1 And Irq12 Latch
6300ESB ICH on the ISA ® bus. On Intel 6300ESB ICH, this is not the case. Therefore, the clearing of the latch must be done through a snoop of port 60h. The waveform which performs this snoop is shown in Figure 13.
Page 121: Advanced Interrupt Controller (Apic) (D29:F5)
• Method of Interrupt Transmission. Interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. The Intel® 6300ESB ICH only supports FSB delivery of interrupts. • Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number.
Page 122: Boot Interrupt
® The Intel 6300ESB ICH’s APIC1 contains a capability to logically OR several of its interrupt inputs together to generate a single interrupt through PIC. This is necessary for systems that do not support the APIC, and for boot. The generated interrupt is routed to IRQ 9.
Page 123: Interrupt Mapping In Non-Apic
4. If IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other ® devices to ensure the proper operation of MMT #2. The Intel 6300ESB ICH does not prevent sharing of IRQ 11.
Page 124: Apic Interrupt Mapping, Apic0 Agent
6. When IRQ11 is used for MMT #2, software should ensure IRQ 11 is not shared with any other ® devices to ensure the proper operation of MMT #2. The Intel 6300ESB ICH does not prevent sharing of IRQ 11.
Page 125: Apic Interrupt Mapping, Apic1 Agent
EOI priority is used to send EOI messages for level interrupts from a local APIC to an I/O APIC. When an agent requests the bus with EOI priority, all other agents requesting the bus with normal priorities will back off. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 126: Arbitration Cycles
® When the Intel 6300ESB ICH detects a bus idle condition on the APIC Bus, and it has an interrupt to send over the APIC bus, it drives a start cycle to begin arbitration, by driving bit 0 to a ‘0’ on an APICCLK rising edge. It then samples bit 1. When Bit 1 was a zero, then a local APIC started arbitration for an EOI message on the same clock edge ®...
Page 127: Eoi Message
NOT(V5) NOT(V4) NOT(V3) NOT(V2) NOT(V1) NOT(V0) NOT(C1) NOT(C0) Check Sum from Cycles 6 - 9 Postamble NOT(A) NOT(A) Status Cycle 0 NOT(A1) NOT(A1) Status Cycle 1 Idle ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 128: Short Message
Cycle 19 and 20 indicates the status of the message, i.e., accepted, check sum error, retry or error. The following table shows the status signal combinations and their meanings for all delivery modes. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 129: Apic Bus Status Cycle Definition
Status cycle 19 identifies when there is a Focus processor (10) and a status value of 11 in cycle 20 indicates the need for lowest priority arbitration. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 130: Lowest Priority Message (Without Focus Processor)
“free interrupt slots” will participate in the lowest priority arbitration. 2. Cycles 29 through 32 are used to break tie in case two more processors have lowest priority. The bus arbitration ID's are used to break the tie. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 131: Remote Read Message
Remote read message is used when a local APIC wishes to read the register in another ® local APIC. The I/O APIC in the Intel 6300ESB ICH neither generates or responds to this cycle. The message format is same as short message for the first 21 cycles.
Page 132: Pci Message-Based Interrupts
0000111. The MESSAGE_DATA will be a 32-bit value, although only the lower 5 bits are used. ® 3. When the PRQ bit in the APIC Version Register is set, the Intel 6300ESB ICH positively decodes the cycles (as a slave) in Medium time.
Page 133: Registers And Bits Associated With Pci Interrupt Delivery
For processors that support Processor System Bus interrupt delivery, the Intel 6300ESB ICH has an option to let the integrated I/O APIC behave as an I/O (x) APIC. In this case, it will deliver interrupt messages to the processor in a parallel manner, ®...
Page 134: Interrupt Message Address Format
System Bus messages as a SMI in which case the processor treats the incoming ® interrupt as a SMI instead of as an interrupt. This does not mean that the Intel ® 6300ESB ICH has any way to have a SMI source from the Intel...
Page 135: Interrupt Message Data Format
Serial Interrupt (D31:F0) ® The Intel 6300ESB ICH supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared ® between the host, the Intel 6300ESB ICH, and all peripherals that support serial interrupts.
Page 136: Start Frame
Start Frame. Since the first PCI ® clock of the start frame was driven by the peripheral in this mode, the Intel 6300ESB ICH will drive the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation.
Page 137: Stop Frame Explanation
® The Intel 6300ESB ICH will ignore the state of these interrupts in the serial stream, and will not adjust their level based on the level seen in the serial stream. In addition, the interrupts IRQ14 and IRQ15 from the serial stream are treated differently than their ISA counterparts.
Page 138: Real Time Clock (D31:F0)
When a RAM read from the ten time and date bytes is attempted during an update cycle, the value read will not necessarily represent the true contents of those locations. Any RAM writes under the same conditions will be ignored. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 139: Lockable Ram Ranges
09h) transitions form 99 to 00. Upon detecting the rollover, the Intel 6300ESB ICH will set the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). When the system is in an S0 state, this will cause an SMI#. The SMI# handler may update registers in the RTC RAM that are associated with century value.
Page 140: Configuration Bits Reset By Rtcrst# Assertion
® Clearing CMOS RAM in an Intel 6300ESB ICH-based platform may be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low.
Page 141: Init# Going Active
5—Intel 6300ESB ICH 5.10 Processor Interface (D31:F0) ® The Intel 6300ESB ICH interfaces to the processor with a variety of signals • Standard Outputs to the processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#, CPUSLP# • ® The FERR# input to the Intel 6300ESB ICH has special buffer requirements.
Page 142: Coprocessor Error Timing Diagram
When FERR# is driven active by the processor, IRQ13 goes active ® (internally). When it detects a write to the COPROC_ERR register, the Intel 6300ESB ICH negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive.
Page 143: Nmi Sources
For multiple-CPU (or Multiple-core) configurations in which more than one Stop Grant cycle may be generated, the MCH is expected to count Stop Grant cycles and only pass the last one through to the 6300ESB. This prevents the 6300ESB from getting out of sync with the processor on multiple STPCLK# assertions.
Page 144 In going to the S1 state, multiple Stop-Grant cycles will be generated by the CPUs. The Intel 6300ESB also has the option to assert the CPU’s SLP# signal (CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the transition to the S1 state), the CPUs will not be executing code that is likely to delay the Stop-Grant cycles.
Page 145: Power Management (D31:F0)
— ACPI G2/S5 state - Soft Off(SOFF) — Power Failure Detection and Recovery — Supports new output signal - SLP_S4# • Streamlined Legacy Power Management Support for APM-Based Systems • Support for Prescott Processor ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 146: General Power States For Systems Using Intel 6300Esb Ich
® Intel 6300ESB ICH—5 ® 5.11.2 Intel 6300ESB ICH Power States and Transition Rules ® Table 62 shows the power states defined for Intel 6300ESB ICH-based platforms. The state names generally match the corresponding ACPI states. ® Table 62. General Power States for Systems Using Intel...
Page 147: State Transition Rules For Intel 6300Esb I/O Controller Hub
For example, in going from S0 to S1, it may appear to pass through the G0/S0/ C2 states. These intermediate transitions and states are not listed in the table. ® Table 63. State Transition Rules for Intel 6300ESB I/O Controller Hub Present Transition Trigger...
Page 148: System Power Plane
® 5.11.4 Intel 6300ESB ICH Power Planes ® The Intel 6300ESB ICH power planes were previously defined in Section 4.1, “Power Planes”. ® Although not specific power planes within the Intel 6300ESB ICH, there are many interface signals that go to devices that may be powered down. These include: •...
Page 149: Causes Of Sci
® Upon any SMI# event, the Intel 6300ESB ICH will assert SMI# to the processor, which will cause it to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit (bit 1) is set, SMI# will go inactive for a minimum of four PCI clocks.
Page 150: Causes Of Smi
X in the Synch column are treated as Synchronous.Synchronous SMI#s are not possible in IA64 platforms, since they do not support the SMI# signal. 4. NMI2SMI_STS is not gated by TCO_EN. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 151: Causes Of Tco Smi
Changes of the BIOSWP bit from 0 BLD = 1 BIOSWR_STS to 1 Write attempted to BIOS BIOSWP = 1 BIOSWR_STS Section 5.12.3, “TCO Theory of Operation” for details on the TCO SMI# causes. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 152: Break Events
® Intel 6300ESB ICH. ® A C1 or C2 state ends due to a break event. Based on the break event, the Intel 6300ESB ICH returns the system to C0 state. Table 68 lists the possible break events from C2 states. The break events from C1 are indicated in the processor’s datasheet.
Page 153: Ds November
6300ESB ICH ® 5. The Intel 6300ESB ICH waits at least 180 ns to 8 PCI clocks (240 ns) after deasserting STPCLK# and then starts using the FERR# signal for an indication of a ® floating point error. The maximum time that the Intel...
Page 154: Latching Processor I/F Signals With Stopclk
The Host controller must post Stop-Grant cycles in such a way that the processor ® gets an indication of the end of the special cycle prior to the Intel 6300ESB ICH observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a sufficient period after the processor observes the response phase.
Page 155: Sleep States
® active, the Intel 6300ESB ICH will still drive SMI# active. This is because the STPCLK# was obviously too late to be recognized at the instruction boundary. The I/O cycles that may cause SMI# include: writes to the APM register (B2h), accesses to 60/ 64h when “Legacy USB KBC scheme”...
Page 156: Sleep Types
Sleep Comment Type ® The Intel 6300ESB ICH asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This will lower the processor’s power consumption. No snooping is possible in this state. ® The Intel 6300ESB ICH asserts SLP_S3#. The SLP_S3# signal will control the power to non-critical circuits.
Page 157: Sx-G3-Sx, Handling Power Failures
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. ® The Intel 6300ESB ICH monitors both PWROK and RSMRST# to detect for power failures. When PWROK goes low, the PWROK_FLR bit is set. When RSMRST# goes low, PWR_FLR is set.
Page 158: Transitions Due To Power Failure
5.11.8 Thermal Management ® The Intel 6300ESB ICH has mechanisms to assist with managing thermal problems in the system. 5.11.8.1 THRM# Signal The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# ®...
Page 159: Thrm# Override Software Bit
® When the Intel 6300ESB ICH is in the C2, or S1–S5 states, then no throttling will be caused by the THRM# signal being active. 5.11.8.3 THRM# Override Software Bit The FORCE_THTL bit allows the BIOS to force passive cooling, just as though the ®...
Page 160: Transitions Due To Power Button
Power Button may wake the system, but the Sleep Button cannot. ® Although the Intel 6300ESB ICH does not include a specific signal designated as a Sleep Button, one of the GPIO signals may be used to create a “Control Method” Sleep Button. See the ACPI specification for implementation details.
Page 161: Transitions Due To Ri# Signal
® Intel 6300ESB ICH will attempt to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. When the SMBus is idle when the pin is detected active, the reset will occur immediately, otherwise the counter will start. When at any point during the count the SMBus goes idle the reset will occur.
Page 162: Alt Access Mode
® longer executing cycles properly. Therefore, when THRMTRIP# fires and the Intel 6300ESB ICH is relying on state machine logic to perform the power down, the state machine may not be working and the system will not power down. ®...
Page 163: Write Only Registers With Read Paths In Alt Access Mode
DMA Chan 6 base address high byte byte NOTES: 1. The OCW1 register must be read before entering ALT access mode. 2. Bits 5, 3, 1, and 0 return zero. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 164: Programmable Interrupt Controller (Pic) Reserved Bits
PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in the following table. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 165: Pic Reserved Bits Return Values
® maintained to system memory, the Intel 6300ESB ICH resume well, and to any other circuits that need to generate Wake signals from the STR state. Cutting power to the core may be done through the power supply, or by external FETs to the motherboard.
Page 166 PWROK goes high, then this is a full power failure and the reboot policy is controlled by the AFTERG3 bit. 2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that ® are less than one RTC clock period may not be detected by the Intel 6300ESB ICH. 5.11.11.3VRMPWRGD Signal ®...
Page 167: Intel ® 6300Esb Ich Clock Inputs
Cx states. Stopped in S3 ~ S5 based on SLP_S3# assertion. This signal is not 5V tolerant. ® Free-running PCI Clock to the Intel 6300ESB ICH. Provides timing for all transactions on the internal primary PCI bus, as well as units inside...
Page 168: Legacy Power Management Theory Of Operation
® The Intel 6300ESB ICH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, will generate an SMI# once per minute. The SMI handler may check for system activity by reading the DEVACT_STS register. When none of the system bits are set, the SMI handler may increment a software counter.
Page 169: Tco Signal Usage
The Intel 6300ESB ICH supports TCO compatible mode connectivity. The Intel 6300ESB ICH supports LAN controllers. A LAN controller can be used to receive or retrieve TCO message or information on Host SMBus if needed. In Legacy TCO mode ®...
Page 170: Tco Theory Of Operation
2 times caused the SECOND_TO_STS bit to be set), the ® Intel 6300ESB ICH will set the CPU MISSING EVENT bit for the TCO message. 5.12.3.3 Handling an OS Lockup Under some conditions, the OS may lock up. To handle this, the TCO Timer is used with the following algorithm: 1.
Page 171: Detecting Improper Fwh Programming
® The Intel 6300ESB ICH has an input signal, INTRUDER#, that may be attached to a switch that is activated by the system’s case being open. This input has a two RTC clock debounce. When INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO_STS register.
Page 172: Event Transitions That Cause Messages
® The Intel 6300ESB ICH may function directly with a LAN Controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state.
Page 173 ® 1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The Intel ® 6300ESB ICH may send up to 1 Event message to the LAN. The Intel 6300ESB ICH will then attempt to reboot the processor. 2. When the reboot at step 1 is successful then the BIOS should clear the SECOND_TO_STS bit.
Page 174 PWROK low or through the message on the SMBus slave I/F), the Intel 6300ESB ICH will attempt to reset the system. ® 9. When step 8 (reset attempt) is successful, then the BIOS will be run. The Intel 6300ESB ICH will continue sending heartbeats until the BIOS clears the SECOND_TO_STS bit. ®...
Page 175 6300ESB ICH will send a Heartbeat message every Heartbeat Period (30-32 seconds). ® 2. When an event occurs prior to the system being shut down, the Intel 6300ESB ICH will immediately send another Event message with the next (incremented) sequence number.
Page 176: Gpio Implementation
3. Core-well GPIO are 5V tolerant, except for GPIO[7:6] and [32:43]. 4. Resume-well GPIO are not 5V tolerant. 5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 177 3. Core-well GPIO are 5V tolerant, except for GPIO[7:6] and [32:43]. 4. Resume-well GPIO are not 5V tolerant. 5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 178: Power Wells
® Some Intel 6300ESB ICH GPIOs may be connected to pins on devices that exist in the core well. When these GPIOs are outputs, there is a danger that a loss of core power ®...
Page 179: Pio Transfers
® The Intel 6300ESB ICH IDE controller supports both legacy mode and PCI native mode. In legacy mode, the Command and Control Block registers are accessible at fixed I/O addresses, may not be accessed through the I/O BARs. These blocks are decoded when I/O space is enabled through the P-ATA function’s configuration space...
Page 180: Ide Legacy I/O Ports: Command Block Registers (Cs1X# Chip Select)
Status Command ® NOTE: For accesses to the Alt Status register in the Control Block, the Intel 6300ESB ICH must always force the upper address bit (PDA[2] or SDA[2]) to 1 in order to ensure proper native mode decode by the IDE device. Unlike the legacy mode fixed address location, the native mode address for this register may contain a 0 in address bit 2 when ®...
Page 181: Ide Transaction Timings (Pci Clocks)
® on the PCI bus after the data is received by the Intel 6300ESB ICH. The Intel 6300ESB ICH will then run the IDE cycle to transfer the data to the drive. When the ® Intel 6300ESB ICH write buffer is non-empty and an unrelated (non-data or opposite channel) IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is transferred to the drive.
Page 182: Physical Region Descriptor Table Entry
® The Intel 6300ESB ICH may act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master channels are provided, one channel for each IDE connector (primary and secondary). By performing the IDE data transfer as a PCI Bus master, the ®...
Page 183 5.14.3.4 Interrupts Legacy Mode: ® The Intel 6300ESB ICH is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt. This connection is done from the ISA pin, before any mask registers. This implies the following: •...
Page 184 Interrupt and Active bits in the Status Register after a DMA transfer has started. ® During concurrent DMA or Ultra ATA transfers, the Intel 6300ESB ICH IDE interface will arbitrate between the primary and secondary IDE cables when a PRD expires.
Page 185: Interrupt/Active Bit Interaction Definition
These pins have similar characteristics to their ISA counterparts in terms of when data is valid relative to strobe edges, and the polarity of the strobes, however ® the Intel 6300ESB ICH does not use the 8237 for this mode. ® Intel 6300ESB I/O Controller Hub...
Page 186: Ultraata/33 Control Signal Redefinitions
DIOR# signal is redefined as STROBE for transferring data from the Intel 6300ESB ® ICH to the IDE device (write). It is the data strobe signal driven by the Intel 6300ESB ICH on which data is transferred during each rising and falling edge transition.
Page 187 The data transfer phase continues the burst transfers with the data transmitter (Intel 6300ESB ICH - writes, IDE device - reads) providing data and toggling STROBE. Data is transferred (latched by receiver) on each rising and falling edge of STROBE. The transmitter may pause the burst by holding STROBE high or low, resuming the burst by again toggling STROBE.
Page 188: Ultra Ata/66 Protocol
® Intel 6300ESB ICH—5 6300ESB ICH will drive the CRC value onto the DD[15:0] signals. It is then latched by ® the IDE device on deassertion of DDACK#. The IDE device compares the Intel 6300ESB ICH CRC value to its own and reports an error if there is a mismatch.
Page 189: Sata Host Controller (D31:F2)
5.15.2.1 Standard ATA Emulation ® The Intel 6300ESB ICH contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO and DMA data transfers, resets, and interrupts are all emulated.
Page 190: Sata Power States
6300ESB ICH—5 5.15.4.1 Power State Mappings ® The following PCI power management states for devices are supported by the Intel 6300ESB ICH SATA Controller: D0 – working D3 – very deep sleep. This state is split into two sub-states, D3...
Page 191 To block accesses to the native IDE ranges, software must use the generic Power Management control registers described in Section 8.8.1.7, “Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for Devices 4-7 (PM— D31:F0)”. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 192: Sata Msi Vs. Pci Irq Actions
® The Intel 6300ESB ICH provides three timers. The three timers are implemented as a single counter each with its own comparator and value register. Each timer’s counter increases monotonically. Each individual timer may generate an interrupt when the value in its value register matches the value in the main counter.
Page 193: Legacy Routing
Software may change the value. Warning:Software must be careful when programming the comparator registers. When the value written to the register is not sufficiently far in the future, the counter ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 194 1. Set TIMER0_VAL_SET_CNF bit 2. Set the lower 32 bits of the Timer0 Comparator Value register 3. Set TIMER0_VAL_SET_CNF bit 4. Set the upper 32 bits of the Timer0 Comparator Value register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 195: Enabling The Timers
When a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 196: Frame List Pointer Bit Description
TD (Transfer Descriptor) or a QH (Queue Head). This allows the ® Intel 6300ESB ICH to perform the proper type of processing on the item after it is fetched. 1 = QH 0 = TD ®...
Page 197: Transfer Descriptor
6300ESB ICH that there are no more valid entries in the queue. ® A TD encountered outside of a queue context with the T bit set informs the Intel 6300ESB ICH that this is the last TD in the frame.
Page 198: Td Control And Status
® There are special restrictions on schedule placement for low speed TDs. When an Intel 6300ESB ICH root hub port is connected to a full speed device and this bit is set to a 1 ® for a low speed transaction, the Intel 6300ESB ICH sends out a low speed preamble ®...
Page 199 The Active bit is also set to 0 when a stall handshake is received from the endpoint. ® 1 = Set to 1 by software to enable the execution of a message transaction by the Intel 6300ESB ICH. Stalled: ®...
Page 200: Td Token
Description Bus Turn Around Time-out (BTTO): ® 1 = This bit is set to a 1 by the Intel 6300ESB ICH during status updates to indicate that a bus time-out condition was detected for this USB transaction. This time-out is specially defined as not detecting an IDLE-to ‘K’ state Start of Packet (SOP) transition from 16 to 18 bit times after the SE0-to-IDE transition of previous End of Packet (EOP).
Page 201: Td Buffer Pointer
1 = QH ® Terminate (T): This bit indicates to the Intel 6300ESB ICH that this is the last QH in the schedule. When there are active TDs in this queue, they are the last to be executed in this frame.
Page 202: Data Transfers To/From Main Memory
® 1. The Intel 6300ESB ICH first fetches an entry from the Frame List. This entry has three fields. Bit 0 indicates whether the address pointer field is valid. Bit 1 indicates whether the address points to a Transfer Descriptor or to a queue head. The third field is the pointer itself.
Page 203 TD mode. ® 1. The Intel 6300ESB ICH fetches TD or QH from the current Link Pointer. 2. When a QH, go to 1 to fetch from the Queue Element Link Pointer. When inactive, go to 12.
Page 204: Command Register, Status Register And Td Status Bit Interaction
6300ESB ICH—5 5.17.3.3 Command Register, Status Register, and TD Status Bit Interaction Table 94. Command Register, Status Register and TD Status Bit Interaction ® Intel 6300ESB ICH USB Status Register TD Status Register Condition Actions Actions Clear Active bit and set...
Page 205: Example Queue Conditions
When this occurs, a new Q Context is entered and the Q Context just exited is NULL ® (The Intel 6300ESB ICH will not update the vertical pointer field). The far right QH is an example of a frame ‘termination’ node. Since its horizontal link ®...
Page 206: Queue Advance Criteria
6300ESB ICH is currently ® processing a queue, and the advance criteria are met, and the Vf bit is set, the Intel 6300ESB ICH follows the TD’s link pointer to the next schedule work item. Note that regardless of traversal model, when the advance criteria are met, the successful TD’s link pointer is written back to the QH’s Queue Element link pointer.
Page 207: Usb Schedule List Traversal Decision Table
In Queue. Use QE.LP to get TD. Execute TD. Update QE.LP with TD.LP. Use QH.LP to get next (QH+QE). In Queue. Empty queue. Use QH.LP to get next (QH+QE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 208: Usb Data Encoding
Field formats for the token, data, and handshake packets are described in the following section. The effects of NRZI coding and bit stuffing have been removed for the sake of clarity. All packets have distinct start and end of packet delimiters. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 209: Pid Format
® 5—Intel 6300ESB ICH Table 97. PID Format Data Sent Data Sent PID 0 NOT(PID 0) PID 1 NOT(PID 1) PID 2 NOT(PID 2) PID 3 NOT(PID 3) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 210: Pid Types
Function endpoints are addressed using two fields: the function address field and endpoint field. Table 99. Address Field Data Sent Data Sent ADDR 0 ADDR 4 ADDR 1 ADDR 5 ADDR 2 ADDR 6 ADDR 3 Address Field ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 211: Endpoint Field
IN PIDs define a data transaction from a function to the ® ® Intel 6300ESB ICH. OUT and SETUP PIDs define data transactions from the Intel 6300ESB ICH to a function. ® Intel 6300ESB I/O Controller Hub...
Page 212: Token Format
PID, which has its own check field. Table 103. Data Packet Format Packet Width 8 bits 0-1023 DATA bytes CRC16 16 bits ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 213: Handshake Responses
When the function may ® transmit data, it will issue the data packet. The Intel 6300ESB ICH, as the USB host, may return only one type of handshake on an IN transaction, an ACK. When it receives a corrupted data, or cannot accept data due to a condition such as an internal buffer overrun, it discards the data and issues no response.
Page 214: Usb Interrupts
® A CRC/Time-Out error occurs when a packet transmitted from the Intel 6300ESB ICH ® to a USB device or a packet transmitted from a USB device to the Intel 6300ESB ICH ® generates a CRC error. The Intel 6300ESB ICH is informed of this event by a time-out ®...
Page 215 6300ESB ICH (due to incorrect schedule ® for instance), the Intel 6300ESB ICH will force a bit stuff error followed by an EOP and the start of the next frame. Stalled This event indicates that a device/endpoint returned a STALL handshake during a transaction or that the transaction ended in an error condition.
Page 216: Usb Power Management
This interrupt cannot be disabled through the Interrupt Enable register. Host System Error ® The Intel 6300ESB ICH sets this bit to 1 when a PCI Parity error, PCI Master Abort, or ® PCI Target Abort occur. When this error occurs, the Intel 6300ESB ICH clears the Run/ Stop bit in the Command register to prevent further execution of the scheduled TDs.
Page 217: Usb Legacy Keyboard/Mouse Control Register Bit Implementation
A20Gate Pass-Through Enable (bit 5) in all of the host controllers. ® When any of these bits in the three host controllers is set, the Intel ORed together 6300ESB ICH will enable the Legacy Keyboard A20Gate Pass-through A20Gate Pass- to enable the sequence.
Page 218 ANDing the four enables (60R, 60W, 64R, 64W) with the four types of accesses to determine when 8042CS should go active. An additional term is required for the “Pass-through” case. The state table for the diagram is shown in Table 106. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 219: Usb Legacy Keyboard Flow Diagram
Decoder EN_SMI_ON_60R Read, W rite NOT (North PCI gnt) North PCI cycle Same for 60W , 64R, 64W EN_PIRQD# To PIRQD# To "Caused By" Bit USB_IRQ Clear USB_IRQ EN_SMI_ON_IRQ ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 220: Usb Legacy Keyboard State Transitions
Config Register is set, then SMI# should be generated. GateState Just stay in same state. Generate an SMI# when GateState2 64h / Read enabled in Bit 2 of Config Register. PSTATE remains 1. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 221: Uhci Vs. Ehci
USB port is controlled by one of the UHCI controllers or by the ® EHCI controller. A USB 2.0 based Debug Port is also implemented in the Intel 6300ESB ICH. A summary of the key architectural differences between the USB UHCI host controllers and the USB EHCI host controller are shown in the table below: Table 107.
Page 222: 5.18.2.4 Ehc Resets
® In addition to the standard Intel 6300ESB ICH hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3hot device power management state to the D0 state. The effects of each of these resets are: ®...
Page 223: Data Structures In Main Memory
This summary is provided to help explain the reasons for the reset policies. 5.18.3 Data Structures in Main Memory See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.96. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 224: 5.18.4.1.1 Read Policies For Periodic Dma
USB 2.0 Enhanced Host Controller DMA ® The Intel 6300ESB ICH USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. USB 2.0 Debug Port (see Section 5.18.11, “USB 2.0 EHCI Based Debug Port”)
Page 225: 5.18.4.1.2 Write Policies For Periodic Dma
Pointers, and Alt. Next qTD Pointers are re-written Write with the original value. ® The Intel 6300ESB ICH breaks data writes down into In Data Up to 257 16 DWORD aligned chunks. NOTES: 1. The Periodic DMA Engine (PDE) will only generate writes after a transaction is executed on USB.
Page 226: 5.18.4.2.1 Read Policies For Asynchronous Dma
Queue Head Only the 64-bit addressing format is supported. ® The Intel 6300ESB ICH breaks large read requests Out Data Up to 129 down into smaller aligned read requests based on the setting of the Read Request Max Length field.
Page 227: Write Policies For Asynchronous Dma
® The Intel 6300ESB ICH may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in...
Page 228: Aborts On Usb Ehci-Initiated Memory Reads
6300ESB ICH delivers interrupts using PIRQ#[H]. • ® The Intel 6300ESB ICH does not modify the CERR count on an Interrupt IN when the “Do Complete-Split” execution criteria are not met. • For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get set on a control-structure-fetch that fails the late-start test.
Page 229 All core well logic is reset in the S3/S4/S5 states (core power turns off). 5.18.8.5 Low-power system Considerations ® The Intel 6300ESB ICH USB EHCI implementation does not behave differently in low power configurations. However, some features may be especially useful for the low power configurations. •...
Page 230: Interaction With Classic Host Controllers
® in the Intel 6300ESB ICH. The USB UHCI Controller at D29:F0 shares ports 0 and 1 and the USB UHCI Controller at D29:F1 shares ports 2 and 3 with the EHCI Controller. There is very little interaction between the USB EHCI and the USB UHCI controllers other than the muxing control which is provided as part of the EHCI Controller.
Page 231: Device Connects
6300ESB ICH ® The Intel 6300ESB ICH also allows the USB Debug Port traffic to be routed in and out of Port #0. When in this mode, the Enhanced Host Controller is the owner of Port #0. 5.18.9.2 Device Connects Section 4.2 of the EHCI Specification describes the details of handling Device Connects.
Page 232: 5.18.9.4 Effect Of Resets On Port-Routing Logic
5.18.11 USB 2.0 EHCI Based Debug Port ® The Intel 6300ESB ICH supports the elimination of the legacy COM ports by providing the ability for new debugger software to interact with devices on a USB EHCI port. High-level restrictions and features are: •...
Page 233: Usb Debug Port Behavior
Stop Debug port is not being used. Normal operation. Debug port is not being used. Normal operation. Debug port in Mode 1. SYNC keep alives sent plus debug traffic. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 234 — TOKEN_PID_CNT[7:0] — SEND_PID_CNT[15:8] — DATA_LEN_CNT — WRITE_READ#_CNT (Note: This will always be 1 for OUT transactions.) — GO_CNT (Note: This will always be 1 to initiate the transaction.) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 235 — WRITE_READ#_CNT (Note: This will always be 0 for IN transactions.) — GO_CNT (Note: This will always be 1 to initiate the transaction.) 2. The debug port controller sends a token packet consisting of: a. SYNC b. TOKEN_PID_CNT field ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 236: Usb_Address_Cnt Field
Section 11.2.1.3, “Offset 04 - 07h: HCSPARAMS—Host Controller Structural Parameters” for information regarding offset 04h. This 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). Debug Software Startup with Non-Initialized EHCI ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 237: Smbus Controller Functional Description (D31:F3)
5.19.1 Overview ® The Intel 6300ESB ICH provides an SMBus 2.0 compliant Host Controller as well as an SMBus slave interface. The host controller provides a mechanism for the processor to initiate communications ® with SMBus peripherals (slaves). The Intel...
Page 238: Host Controller
® The Slave Interface allows an external master to read from or write to the Intel 6300ESB ICH. Write cycles may be used to cause certain events or pass messages, and ® the read cycles may be used to determine the state of various status bits. The Intel ®...
Page 239: Quick Protocol
KILL bit in the Host Control Register while the command is running, the ® transaction will stop and the FAILED bit will be set. When the KILL bit is set, the Intel 6300ESB ICH will abort current transaction by asserting SMBCLK low for greater than the timeout period, assert a STOP condition and then releases SMBCLK and SMBDATA.
Page 240: Send/Receive Byte Protocol With Pec
Table 119. Write Byte/Word Protocol with PEC Write Byte Protocol Write Word Protocol Description Description Start Start 2–8 Slave Address - 7 bits 2–8 Slave Address - 7 bits Write Write ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 241 Stop Read Byte/Word ® Reading data is slightly more complicated than writing data. First the Intel 6300ESB ICH must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data.
Page 242: Read Byte/Word Protocol Without Pec
Data Byte Low from slave - 8 bits Acknowledge Acknowledge 39–46 PEC from slave 39–46 Data Byte High from slave - 8 bits NOT Acknowledge Acknowledge Stop 48–55 PEC from slave NOT acknowledge Stop ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 243: Process Call Protocol Without Pec
The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. ® When programmed for the Process Call command, the Intel 6300ESB ICH transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers.
Page 244 ® The Intel 6300ESB ICH contains a 32-byte buffer for read and write data which may be enabled by setting bit ‘1’ of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data ®...
Page 245: Block Read/Write Protocol Without Pec
® changes slightly. The Intel 6300ESB ICH will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the DATA0 register. However, it will not send the contents of the DATA0 register as part of the message.
Page 246 C Block Read ® This command allows the Intel 6300ESB ICH to perform block reads to certain I devices, such as serial E PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I C “Combined...
Page 247 Stop ® The Intel 6300ESB ICH will continue reading data from the peripheral until the NAK is received. Block Write-Block Read Process Call The Block Write-Block Read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message.
Page 248: Block Write-Block Read Process Call Protocol With/Without Pec
Acknowledge from master … … Data Byte Count (N) from slave – 8 bits Acknowledge from master (Skip if no PEC) PEC from slave (Skip if no PEC) NOT acknowledge Stop ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 249: Heartbeat For Use With The External Lan Controller
Bus Timing 5.19.4.1 Clock Stretching ® Some devices may not be able to handle their clock toggling at the rate that the Intel 6300ESB ICH as an SMBus master would like. They have the capability of stretching ® the low time of the clock. When the Intel 6300ESB ICH attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time.
Page 250: Interrupts/Smi
® The Intel 6300ESB ICH must monitor the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock may be stretched by an SMBus master when it is not ready to send or receive data.
Page 251: Smbus Slave Interface
SMBALERT# is multiplexed with GPIO[11]. When enabled and the signal is asserted, ® the Intel 6300ESB ICH may generate an interrupt, an SMI# or a wake event from S1 – Note: Any event on SMBALERT# (regardless whether it is programmed as a GPIO or not), causes the event message to be sent in “heartbeat mode.”...
Page 252: Format Of Slave Write Cycle
Register”) for all others. ® Note: The external microcontroller should not attempt to access the Intel 6300ESB ICH’s SMBus slave logic until 1 second after both: RTEST# is high and RSMRST# is high. When a master leaves the clock and data bits of the SMLink interface at ‘1’ for 50 µs or ®...
Page 253: Command Types
® The Intel 6300ESB ICH will overwrite the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time ®...
Page 254: Format Of Read Command
Reserved 5.19.8.2 Format of Read Command ® The external master performs Byte Read commands to the Intel 6300ESB ICH SMBus Slave I/F. The “Command” field (bits 11-18) indicate which register is being accessed. The Data field (bits 30-37) contains the value that should be read from that register.
Page 255: Data Values For Slave Read Registers
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. ® 1 = BTI Temperature Event occurred. This bit will be set when the Intel 6300ESB ICH’s THRM# input signal is active. Need to take after polarity control.
Page 256: Format Of Host Notify Command
A race condition is possible where the new value ® is being written to the register just at the time it is being read. The Intel 6300ESB ICH will not attempt to cover this race condition (i.e., unpredictable results).
Page 257: Ac'97 Controller Functional Description (Audio D31:F5, Modem D31:F6)
Specification, Version 2.2. For further information on the operation of the AC-link protocol, please see the AC ’97 specification. ® The Intel 6300ESB ICH AC’97 controller features include: • Independent (FDX) channels for mono Line in and out. • Supports 16 bit samples.
Page 258: Features Supported By Intel ® 6300Esb Ich
® Intel 6300ESB ICH—5 ® Table 137 shows a detailed list of features supported by the Intel 6300ESB ICH AC’97 digital controller. ® Table 137. Features Supported by Intel 6300ESB ICH (Sheet 1 of 2) Feature Description • Isochronous low latency bus master memory interface •...
Page 259 ® 5—Intel 6300ESB ICH ® Table 137. Features Supported by Intel 6300ESB ICH (Sheet 2 of 2) Feature Description • Read/write access to modem codec registers 3Ch-58h and vendor registers 5Ah-7Eh • 16-bit mono modem line1 output and input, up to 48 KHz (slot 5) PCI Modem •...
Page 260: Pci Power Management
® Intel 6300ESB ICH—5 ® Figure 23. Intel 6300ESB ICH Based AC’97 Controller Connection to Companion Codec(s) Audio In (Record) Audio Out (Playback) Modem Handset Mic. 5.20.1.1 PCI Power Management This Power Management section applies for all AC’97 controller functions. After a power management event is detected, the AC’97 controller will wake the host system.
Page 261: Ac'97 2.2 Controller-Codec Connection
6300ESB ICH ® The Intel 6300ESB ICH is an AC’97 2.0 compliant controller that communicates with companion codecs through a digital serial link called the AC-link. All digital audio/ modem streams and command/status information is communicated over the AC-link. The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme.
Page 262: Ac-Link Protocol
When BIT_CLK makes no transitions for four consecutive PCI clocks, the Intel 6300ESB ICH assumes the primary codec is not present or not working. It sets bit 28 of the Global Status Register (I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh to prevent system hangs.
Page 263: Ac-Link Output Frame (Sdout)
When a slot ® is tagged invalid with a zero in the corresponding bit position of slot 0, the Intel 6300ESB ICH stuffs the corresponding slot with zeros during that slot’s active time.
Page 264: Output Slot 1: Command Address Port
PCM (.wav) output samples digitally mixed by the host ® processor. The Intel 6300ESB ICH transmits sample streams of 16 bits or 20 bits and stuffs remaining bits with zeros. ® Data in output slots 3 and 4 from the Intel 6300ESB ICH should be duplicated by software when there is only a single channel out.
Page 265: Output Slot 6: Pcm Playback Center Front Channel
6300ESB ICH. 5.20.2.11Output Slots 10-11: Reserved ® Output frame slots 10-11 are reserved and are always stuffed with 0s by the Intel 6300ESB ICH AC’97 controller. 5.20.2.12Output Slot 12: I/O Control Sixteen bits of DAA and GPIO control (output) and status (input) have been directly assigned to bits on slot 12 in order to minimize latency of access to changing conditions.
Page 266 SDIN data stream must follow the AC’97 specification and be MSB justified with all non- valid bit positions (for assigned and/or unassigned time slots) stuffed with zeros. ® AC_SDIN data is sampled by the Intel 6300ESB ICH on the falling edge of BIT_CLK. ® Intel 6300ESB I/O Controller Hub...
Page 267: Input Slot 0: Tag Phase
® Bits [14:3] in slot 0 indicate which slots of the input stream to the Intel 6300ESB ICH contain valid data, just as in the output frame. The remaining bits in this slot are stuffed with zeros.
Page 268: Input Slot 2: Status Data Port
Bit [19:4]: Control Register Read Data Bit [3:0]: Reserved. 5.20.2.17Input Slot 3: PCM Record Left Channel ® Input slot 3 is the left channel input of the codec. The Intel 6300ESB ICH supports ® 16-bit sample resolution. Samples transmitted to the Intel 6300ESB ICH must be in left/right channel order.
Page 269: Output Tag Slot 0
5.20.2.23Register Access ® In the Intel 6300ESB ICH implementation of the AC-link, up to three codecs may be connected to the SDOUT pin. The following mechanism is used to address the primary, secondary, and tertiary codecs individually. The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of slot 1 are used for the register index.
Page 270: Ac-Link Powerdown Timing
BIT_CLK. Once in a low-power mode, the ® Intel 6300ESB ICH provides three methods for waking up the AC-link; external wake event, cold reset and warm reset. Note: Before entering any low-power mode where the link interface to the codec is expected to be powered down while the rest of the system is awake, the software must set the ®...
Page 271: Sdin Wake Signaling
The codec must not respond with the activation of BIT_CLK until AC_SYNC has been sampled low again by the codec. This will prevent the false detection of a new frame. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 272 Note: On receipt of wake up signalling from the codec, the digital controller will issue an interrupt when enabled. Software will then have to issue a warm or cold reset to the codec by setting the appropriate bit in the Global Control Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 273: System Reset
NOTES: ® ® 1. Intel 6300ESB ICH core well outputs are used as strapping options for the Intel 6300ESB ICH, sampled ® during system reset. These signals may have weak pullups/pulldowns on them. The Intel 6300ESB ICH outputs will be driven to the appropriate level prior to AC_RST# being deasserted, preventing a codec from entering test mode.
Page 274: Software Mapping Of Ac_Sdin To Dma Engine
® Intel 6300ESB ICH hardware may set these bits every time register read data is returned from a function 5 read. No special command is necessary to cause the bits to be set. The new driver/BIOS software will read the bits from this register when it cares to, and may ignore it otherwise.
Page 275: Pci Devices And Functions
Register and Memory Mapping ® The Intel 6300ESB ICH contains registers that are located in the processor’s I/O space, memory space and sets of PCI configuration registers that are located in PCI ® configuration space. This chapter details the Intel 6300ESB ICH I/O and memory maps.
Page 276: Pci Devices And Functions
Bus 0: Device 28: Function 0 New: Hub Interface to PCI-X Bridge NOTE: The PCI to LPC bridge contains registers that control LPC, Power Management, System Management, GPIO, CPU Interface, RTC, Interrupts, Timers, DMA. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 277: Pci Configuration Map
PCI Configuration Map ® Each PCI function on the Intel 6300ESB ICH has a set of PCI configuration registers. The register map tables for each function are included at the beginning of each respective chapter. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification, Revision 2.2.
Page 278: Fixed I/O Address Ranges
6300ESB ICH, and will be passed to PCI. When a PCI master ® targets one of the fixed I/O target ranges, it will be positively decoded by the Intel 6300ESB ICH in medium speed. Note: Unclaimed PCI cycles will be subtractively decoded and forwarded to the LPC.
Page 279 ® 6—Intel 6300ESB ICH ® Table 143. Fixed I/O Ranges Decoded by Intel 6300ESB I/O Controller Hub (Sheet 2 of 3) Read Target Write Target Internal Unit Address 38h - 39h Interrupt Controller Interrupt Controller Interrupt 3Ch - 3Dh Interrupt Controller...
Page 280 ® Intel 6300ESB ICH—6 ® Table 143. Fixed I/O Ranges Decoded by Intel 6300ESB I/O Controller Hub (Sheet 3 of 3) Read Target Write Target Internal Unit Address DMA Controller and LPC or 8Ch - 8Eh DMA Controller 08Fh DMA Controller...
Page 281: Variable I/O Decode Ranges
When a cycle is detected on the Hub Interface, the Intel 6300ESB ICH will positively ® decode the cycle. When the response is on the behalf of an LPC device, the Intel 6300ESB ICH will forward the cycle to the LPC. Refer to Table 144 for a complete list of all variable I/O registers.
Page 282 Anywhere in 64K I/O IDE Unit Control Space Native IDE Secondary Anywhere in 64K I/O IDE Unit Command Space Native IDE Secondary Anywhere in 64K I/O IDE Unit Control Space ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 283: Memory Map
Table 145 shows, from the CPU perspective, the memory ranges that the Intel 6300ESB ICH will decode. Cycles that arrive from the Hub Interface that are not directed to any of the internal memory targets that decode directly from Hub Interface ®...
Page 284 PCI and neither by the ® Intel 6300ESB ICH, then the cycle will Master- Abort on PCI NOTES: 1. These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on PCI.
Page 285: Boot-Block Update Scheme
6300ESB ICH supports a “top-block swap” mode that has the Intel 6300ESB ICH swap the top block in the FWH (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the ®...
Page 286 ® Intel 6300ESB ICH—6 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 287: Pci Configuration Registers (D30:F0)
0000h 32-33h IOLIMIT_HI I/O Limit Upper 16 Bits 0000h ® NOTE: Refer to the Intel 6300ESB ICH Specification Update for the most up-to-date value of the Revision ID register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 288: Offset 00 - 01H: Vid-Vendor Id Register (Hub-Pci-D30:F0)
Bits Name Description Access Vendor Identification 15:0 This is a 16-bit value assigned to Intel. Intel VID = 8086h. Number 7.1.2 Offset 02 - 03h: DID—Device ID Register (HUB- PCI—D30:F0) Table 148. Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0)
Page 289: Offset 04 - 05H: Cmd-Command Register (Hub-Pci-D30:F0)
(offset 06h, bit 14) is set. Wait Cycle Control Hardwired to ‘0’ ® 0 = The Intel 6300ESB ICH will ignore parity errors on the Hub Interface. ® 1 = The Intel 6300ESB ICH is allowed to report parity errors Parity Error Response detected on the Hub Interface.
Page 290: Offset 06 - 07H: Pd_Sts-Primary Device Status Register (Hub-Pci-D30:F0)
00h = Fast timing. This register applies to the Hub Interface. ® Since this register applies to the Hub Interface, the Intel 6300ESB ICH must interpret this bit differently than it is in the PCI spec. Master Data Parity Error R/WC 0 = Software clears this bit by writing a ‘1’...
Page 291: Offset 08H: Rid-Revision Identification Register (Hub-Pci-D30:F0)
Description Access ® 8-bit value that indicates the category of bridge for the Intel Sub-Class Code 6300ESB ICH Hub Interface to PCI bridge. The code is 04h indicating a PCI-to-PCI bridge. 7.1.7 Offset 0Bh: BCC—Base-Class Code Register (HUB-PCI—D30:F0) Table 153. Offset 0Bh: BCC—Base-Class Code Register (HUB-PCI—D30:F0)
Page 292: Offset 0Dh: Pmlt-Primary Master Latency Timer Register (Hub-Pci-D30:F0)
Read-Only Offset: Attribute: 8-bit Default Value: Size: Bits Name Description Access This field indicates the bus number of the Hub Interface and Primary Bus Number is hardwired to 00h. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 293: Offset 19H: Sbus_Num-Secondary Bus Number Register (Hub-Pci-D30:F0)
This Master Latency Timer (MLT) controls the amount of time that the Intel 6300ESB ® ICH will continue to burst data as a master on the PCI bus. When the Intel 6300ESB ICH starts the cycle after being granted the bus, the counter is loaded and starts counting down from the assertion of FRAME#.
Page 294: Offset 1Ch: Iobase-I/O Base Register (Hub-Pci-D30:F0)
Description Access 5-bit value that indicates the number of PCI clocks, in 8-clock ® Master Latency Count increments, that the Intel 6300ESB ICH will remain as master of the bus. Reserved Reserved. 7.1.14 Offset 1Ch: IOBASE—I/O Base Register (HUB- PCI—D30:F0) Table 160.
Page 295: Offset 1Dh: Iolim-I/O Limit Register (Hub-Pci-D30:F0)
Signaled Target Abort in the R/WC (RTA) ® Primary Status Register in this device, and the Intel 6300ESB ICH must send the “target abort” status back to the Hub Interface. Signaled Target Abort ® Intel 6300ESB ICH does not generate target aborts.
Page 296: Offset 20 - 21H: Membase-Memory Base Register (Hub-Pci-D30:F0)
6300ESB ICH will forward all Hub Interface memory accesses ® to PCI, the Intel 6300ESB ICH will only use this information for determining when not to accept cycles as a target. This register must be initialized by the configuration software. For the purpose of address decode, address bits AD[19:0] are assumed to be zero.
Page 297: Offset 22 - 23H: Memlim-Memory Limit Register
6300ESB ICH will forward all Hub Interface memory ® accesses to PCI, the Intel 6300ESB ICH will only use this information for determining when not to accept cycles as a target. This register must be initialized by the configuration software. For the purpose of address decode, address bits AD[19:0] are assumed to be FFFFFh.
Page 298: Offset 24H - 25H: Pref_Mem_Base-Prefetchable Memory Base Register (Hub-Pci-D30:F0)
® accesses to PCI, the Intel 6300ESB ICH will only use this information for determining when not to accept cycles as a target. Note: When the Hub Interface is acting as the initiator, it will not respond as a target.
Page 299: Offset 26H-27H: Pref_Mem_Mlt-Prefetchable Memory Limit Register (Hub-Pci-D30:F0)
® accesses to PCI, the Intel 6300ESB ICH will only use this information for determining when not to accept cycles as a target. Note: When the Hub Interface is acting as the initiator, it will not respond as a target.
Page 300: (Hub-Pci-D30:F0)
Default Value: Size: Bits Name Description Access Hardwired to 00h. The bridge does not generate interrupts, Interrupt Line Routing and interrupts from downstream devices are routed around the bridge. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 301: Offset 3E - 3Fh: Bridge_Cnt-Bridge Control Register (Hub-Pci-D30:F0)
® Sets the maximum number of PCI clock cycles that the Intel 6300ESB ICH waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the delayed transaction completion is at the head of the queue. When the...
Page 302 0 = The Intel 6300ESB ICH deasserts PCIXSBRST# ® This bit controls the behavior of the Intel 6300ESB ICH when a master abort occurs on a transaction that crosses the Hub Interface-PCI bridge in either direction. The default is 0.
Page 303 6300ESB ICH ignores this bit. However, this bit is ® read/write for software compatibility. Since the Intel 6300ESB ICH forwards all I/O cycles that are not in the USB, ISA Enable AC’97, or IDE ranges to PCI, this bit would have no effect.
Page 304: Offset 40 - 43H: Hi_Cmd-Hub Interface Command Control Register
19:1 ® Hub Interface Timeslice time-slice is immediately expired and that the Intel 6300ESB ICH will allow the other master’s request to be serviced after every message. 15:1 This field is hardwired to 00b, indicating that the Hub HI Width Interface is eight bits wide.
Page 305: Offset 44 - 45H: Device_Hide-Secondary Pci Device Hiding Register (Hub-Pci-D30:F0)
PCI IDSEL pin does not ® assert. The Intel 6300ESB ICH supports the ability to hide four external devices (0 through 3). Hiding a PCI device may be useful for debugging, bug work-arounds, and system management support.
Page 306: Offset 50 - 51H: Cnf-Intel® 6300Esb Ich Configuration Register (Hub-Pci-D30:F0)
® Intel 6300ESB ICH—7 ® 7.1.27 Offset 50 - 51h: CNF—Intel 6300ESB ICH Configuration Register (HUB-PCI—D30:F0) Table 173. Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register (HUB-PCI—D30:F0) Device: Function: 50-51h Read/Write Offset: Attribute: 1400h 16-bit Default Value: Size: Bits...
Page 307: Offset 58 - 5Bh: D30_Pne — Perr#_Nmi_Enable Register (Hub-Pci—D30:F0)
Once enabled, this bit should not change. In addition to setting this bit, you also must set bit 12 of D30_F0 Bridge Control Register. See section Section 18.6.1.21. Default = 0 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 308: (Hub-Pci-D30:F0)
Offset 70h: MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0) ® MTT is an 8-bit register that controls the amount of time that the Intel 6300ESB ICH’s arbiter allows a PCI initiator to perform multiple back-to-back transactions on the PCI ® bus. The Intel 6300ESB ICH’s MTT mechanism is used to ensure a fair share of the...
Page 309: Offset 82H: Pci_Mast_Sts-Pci Master Status Register (Hub-Pci-D30:F0)
Reserved. SERR# Enable on 0 = Disable. ® Receiving Target Abort 1 = Enable. When SERR_EN is set, the Intel 6300ESB ICH (SERR_RTA_EN) will report SERR# when SERR_RTA is set. Reserved. Bit 1 was the SERR# Enabled for Delayed Reserved Transaction Timeout, see Section 7.1.24, “Offset 3E - 3Fh:...
Page 310: Offset 92H: Err_Sts-Error Status Register (Hub-Pci-D30:F0)
0 = This bit is cleared by writing a 1. ® ® SERR# Due to Received 1 = Intel 6300ESB ICH sets this bit when the Intel Target Abort 6300ESB ICH receives a target abort. When SERR_EN, ® (SERR_RTA) the Intel 6300ESB ICH will also generate an SERR# when SERR_RTA is set.
Page 311: Pci Configuration Registers (D31:F0)
Device 31 Error Status 90-91h PCI_DMA_CFG PCI DMA Configuration 0000h ® NOTE: Refer to the Intel 6300ESB ICH Specification Update for the most up-to-date value of the Revision ID register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 312: Offset 00 - 01H: Vid-Vendor Id Register (Lpc I/F-D31:F0)
8086h 16-bit Default Value: Size: Core Lockable: Power Well: Bits Name Description Access 15:0 Vendor ID Value This is a 16-bit value assigned to Intel. Intel VID = 8086h ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 313: Offset 02 - 03H: Did-Device Id Register (Lpc I/F-D31:F0)
Core Lockable: Power Well: Bits Name Description Access ® This is a 16-bit value assigned to the Intel 6300ESB ICH LPC 15:0 Device ID Value Bridge. 8.1.3 Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) Table 183. Offset 04 - 05h: PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Page 314: Offset 06 - 07H: Pcista-Pci Device Status (Lpc I/F-D31:F0)
0 = This bit is cleared by software writing a 1 to the bit position. ® 1 = Set by the Intel 6300ESB ICH n the SERR_EN bit is set SSE: Signaled System ® and the Intel 6300ESB ICH generates an SERR# on Error function 0.
Page 315: Offset 08H: Rid-Revision Id Register (Lpc I/F-D31:F0)
Bits Name Description Access ® Refer to the Intel 6300ESB ICH Specification Update for the Revision ID Value most up-to-date value of the Revision ID Register. 8.1.6 Offset 09h: PI—Programming Interface (LPC I/F— D31:F0) Table 186. Offset 09h: PI—Programming Interface (LPC I/F—D31:F0)
Page 316: Offset 0Bh: Bcc-Base-Class Code Register (Lpc I/F-D31:F0)
Default Value: Size: Bits Name Description Access Multi-Function Device This bit is 1 to indicate a multi-function device. 7-bit field identifies the header layout of the configuration Header Type space. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 317: Offset 40 - 43H: Pmbase-Acpi Base Address (Lpc I/F-D31:F0)
Table 191. Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) (Sheet 1 of Device: Function: Read/Write Offset: Attribute: 8-bit Default Value: Size: Core Lockable: Power Well: Bits Name Description Access Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 318 10, or 11, the APIC should be programmed for active- high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 319: Offset 4E - 4Fh: Bios_Cntl (Lpc I/F-D31:F0)
When this bit is written from a 0 to a 1 and Enable BIOS lock Enable (BLE) is also set, an SMI# is generated. This ensures that only SMI code may update BIOS. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 320: Offset 54H: Tco_Cntl-Tco Control (Lpc I/F-D31:F0)
SCI Map IRQ9 IRQ10 IRQ11 Reserved IRQ20 (Only available when APIC enabled) IRQ21 (Only available when APIC enabled) IRQ22 (Only available when APIC enabled) IRQ23 (Only available when APIC enabled) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 321: Offset 58H - 5Bh: Gpio_Base-Gpio Base Address (Lpc I/F-D31:F0)
This bit enables/disables decode of the I/O range pointed to by the GPIO base register and enables/disables the GPIO function. GPIO_EN: GPIO Enable 0 = Disable. 1 = Enable. Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 322: Offset Pirqa - 60H: Pirq[N]_Rout-Pirq[A,B,C,D] Routing Control (Lpc I/F-D31:F0)
0011 = IRQ3 1011 = IRQ11 0100 = IRQ4 1100 = IRQ12 0101 = IRQ5 1101 = Reserved 0110 = IRQ6 1110 = IRQ14 0111 = IRQ7 1111 = IRQ15 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 323: Offset 64H: Serirq_Cntl-Serial Irq Control (Lpc I/F-D31:F0)
Fixed field that indicates the size of the SERIRQ frame. In the ® SIRQSZ: Serial IRQ Intel 6300ESB ICH, this field needs to be programmed to 21 Frame Size frames (0100). This is an offset from a base of 17 which is the smallest data frame size.
Page 324: Offset Pirqe - 68H: Pirq[N]_Rout-Pirq[E,F,G,H] Routing Control (Lpc I/F-D31:F0)
0010 = Reserved1010 = IRQ10 IRQ Routing 0011 = IRQ31011 = IRQ11 0100 = IRQ41100 = IRQ12 0101 = IRQ51101 = Reserved 0110 = IRQ61110 = IRQ14 0111 = IRQ71111 = IRQ15 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 325: Offset 88H: D31_Err_Cfg-Device 31 Error Config Register (Lpc I/F-D31:F0)
Register (LPC I/F—D31:F0) ® Note: This register configures the Intel 6300ESB ICH’s Device 31 responses to various system errors. The actual assertion of SERR# is enabled through the PCI Command register. Table 199. Offset 88h: D31_ERR_CFG—Device 31 Error Config Register (LPC I/F—...
Page 326: Offset 90H - 91H: Pci_Dma_Cfg-Pci Dma Configuration (Lpc I/F-D31:F0)
0 = Software clears this bit by writing a 1 to the bit location. ® SERR_RTA: SERR# Due 1 = The Intel 6300ESB ICH sets this bit when it receives a R/WC ® to Received Target Abort target abort. When SERR_EN, the Intel 6300ESB ICH will also generate an SERR# when SERR_RTA is set.
Page 327: Offset D0H - D3H: Gen_Cntl-General Control Register (Lpc I/F-D31:F0)
6300ESB ICH will not examine the FERR# signal during C2, C3 or C4. FERR#-MUX-EN: CPU ® 1 = Software sets this bit to 1 to enable the Intel 6300ESB Break Event Indication ICH to examine the FERR# signal during a C2, C3 or C4 Enable state as a break event.
Page 328 Access 19:1 SCRATCHPAD These bits are provided for possible future use. ® When set to 1, this bit enables the Intel 6300ESB ICH to MMT_ADDR_EN decode the High Performance Event Timer Memory Address Range selected by bits 16:15 below. This 2-bit field selects 1 of 4 possible memory address ranges for the High Performance Event Timer functionality.
Page 329: Offset D4H: Gen_Sta-General Status (Lpc I/F-D31:F0)
Name Description Access Reserved Reserved. ® 0 = The Intel 6300ESB ICH sampled AC_SDOUT low on the rising edge of PWROK. SAFE_MODE ® 1 = The Intel 6300ESB ICH sampled AC_SDOUT high on the rising edge of PWROK. 0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO timeout).
Page 330: Offset D5H: Back_Cntl-Backed Up Control (Lpc I/F-D31:F0)
Reserved. Reserved Reserved. ® 0 = The Intel 6300ESB ICH will not invert A16. This bit is automatically set to 0 by RTCRST#, but not by any other type of reset. ® 1 = The Intel 6300ESB ICH will invert A16 for cycles going...
Page 331: Offset D8H: Rtc_Conf-Rtc Configuration Register (Lpc I/F-D31:F0)
0 = Disable. U128E: Upper 128-byte 1 = Enables access to the upper 128-byte bank of RTC CMOS Enable RAM. Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 332: Offset E0H: Com_Dec-Lpc I/F Communication Port Decode Ranges (Lpc I/F-D31:F0)
3F8h - 3FFh (COM1) 2F8h - 2FFh (COM2) COMA Decode Range 220h - 227h 228h - 22Fh 238h - 23Fh 2E8h - 2EFh (COM4) 338h - 33Fh 3E8h - 3EFh (COM3) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 333: Offset E1H: Fdd/Lpt_Dec-Lpc I/F Fdd And Lpt Decode Ranges (Lpc I/F-D31:F0)
00 = 378h - 37Fh and 778h - 77Fh LPT Decode Range 01 = 278h - 27Fh (port 279h is read only) and 678h - 67Fh 10 = 3BCh -3BEh and 7BCh - 7BEh 11 = Reserved ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 334: Offset E2H: Snd_Dec-Lpc I/F Sound Decode Ranges (Lpc I/F-D31:F0)
This field determines which range to decode for the Sound Blaster 16 (SB16) Port. 00 = 220h - 233h SB16 Decode Range 01 = 240h - 253h 10 = 260h - 273h 11 = 280h - 293h ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 335: Offset E3H: Fwh_Dec_En1-Fwh Decode Enable 1 Register (Lpc I/F-D31:F0)
Note: This register determines which memory ranges will be decoded on the PCI bus and ® forwarded to the FWH. The Intel 6300ESB ICH will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1. Table 209. Offset E3h: FWH_DEC_EN1—FWH Decode Enable 1 Register (LPC I/F—...
Page 336: Offset E4H - E5H: Gen1_Dec-Lpc I/F Generic Decode Range 1 (Lpc I/F-D31:F0)
The size of this range is 128 bytes. Reserved Reserved. 0 = Disable. GEN1_EN: Generic 1 = Enable the GEN1 I/O range to be forwarded to the LPC I/ Decode Range 1 Enable ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 337: Offset E6H - E7H: Lpc_En-Lpc I/F Enables (Lpc I/F-D31:F0)
1 = Enables the decoding of the MIDI range to the LPC interface. This range is selected in the LPC_Sound MIDI_LPC_EN Decode Range Register. NOTE: This bit is no longer supported and will not be validated. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 338 Range Register. 0 = Disable. 1 = Enables the decoding of the COMA range to the LPC COMA_LPC_EN interface. This range is selected in the LPC_COM Decode Range Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 339: Offset E8H: Fwh_Sel1-Fwh Select 1 Register (Lpc I/F-D31:F0)
IDSEL for two 512 Kbyte FWH memory ranges. The IDSEL programmed in this field addresses the following FWH_C0_IDSEL memory ranges: FFC0 0000h - FFC7 FFFFh FF80 0000h - FF87 FFFFh ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 340: Offset Ech - Edh: Gen2_Dec-Lpc I/F Generic Decode Range 2 (Lpc I/F-D31:F0)
Reserved. Read as 0. Generic I/O Decode Range 2 Enable 0 = Disable. GEN2_EN 1 = Accesses to the GEN2 I/O range will be forwarded to the LPC I/F. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 341: Offset Eeh - Efh: Fwh_Sel2—Fwh Select 2 Register (Lpc I/F—D31:F0)
IDSEL for two 1M FWH memory ranges. The IDSEL programmed in this field addresses the following FWH_40_IDSEL memory ranges: FF40 0000h - FF4F FFFFh FF00 0000h - FF0F FFFFh ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 342: Offset F0H: Fwh_Dec_En2—Fwh Decode Enable 2 Register (Lpc I/F—D31:F0)
Note: This register determines which memory ranges will be decoded on the PCI bus and ® forwarded to the FWH. The Intel 6300ESB ICH will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1. Table 215. Offset F0h: FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC I/F—...
Page 343: Offset F2H: Func_Dis-Function Disable Register (Lpc I/F-D31:F0)
Software sets this bit to disable the AC’97 modem controller function. When disabled, the PCI config space registers for ® that function are not decoded by the Intel 6300ESB ICH. BIOS must not enable I/O or memory address space decode,...
Page 344 SMBus PCI configuration and I/ O space will be disabled. NOTE: Software must always disable all functionality within the function before disabling the configuration space. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 345: Offset F4: Etr1-Pci-X Extended Features Register (Lpc I/F-D31:F0)
F8h-FBh Read-Only Offset: Attribute: 000S 0F66 32-bit Default Value: Size: Core Lockable: Power Well: Bits Name Description Access 31:1 Reserved Reserved. 15:8 Manufacturer 0Fh = Intel Process/Dot Process 859.6 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 346: Dma I/O Registers
Channel 5 DMA Memory Low Page Register Undefined 8Ch - 8Eh 9Ch - 9Eh Reserved Page Registers Undefined Refresh Low Page Register Undefined Channel 4 DMA Base and Current Address Undefined Register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 347 Channel 4-7 DMA Clear Byte Pointer Register Undefined Channel 4-7 DMA Master Clear Register Undefined Channel 4-7 DMA Clear Mask Register Undefined Channel 4-7 DMA Write All Mask Register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 348: Dmabase_Ca-Dma Base And Current Address Registers
Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 349: Dmabase_Cc-Dma Base And Current Count Registers
Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 350: Dmacmd-Dma Command Register
0 = Enable the DMA channel group. Enable 1 = Disable. Disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4. Reserved Reserved. Must be zero. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 351: Dmasta-Dma Status Register
4 is irrelevant: Channel Terminal Count 0 = Channel 0 Status 1 = Channel 1 (5) 2 = Channel 2 (6) 3 = Channel 3 (7) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 352: Dma_Wrsmsk-Dma Write Single Mask Register
11 = Cascade mode This bit controls address increment/decrement during DMA transfers. Address Increment/ 0 = Address increment. (default after part reset or Master Decrement Select Clear) 1 = Address decrement. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 353: Dma Clear Byte Pointer Register
16-bit DMA controller register. The first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 354: Dma Master Clear Register
Ch. #4-7 = DCh xxxx xxxx 8-bit Default Value: Size: Core Lockable: Power Well: Bits Name Description Access No specific pattern. Command enabled with a write to the Clear Mask Register port. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 355: Dma_Wrmsk-Dma Write All Mask Register
Counter 2 Interval Time Status Byte 0XXXXXXXb Format Counter 2 Counter Access Port Register Undefined Timer Control Word Register Undefined Timer Control Word Register Read Back XXXXXXX0b Counter Latch Command ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 356: Tcw -Timer Control Word Register
0 = Binary countdown is used. The largest possible binary count is 2 16 Binary/BCD Countdown Select 1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 10 4 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 357: Rdbk_Cmd-Read Back Command
(read, write, or programming operations for other counters may be inserted between the reads). When a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 358: Ltch_Cmd-Counter Latch Command
Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns the following: ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 359: Sbyte_Fmt—Interval Timer Status Byte Format Register
100 = Mode 4: Software triggered strobe 101 = Mode 5: Hardware triggered strobe This bit reflects the current countdown type. Countdown Type Status 0 = Binary countdown 1 = Binary Coded Decimal (BCD) countdown. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 360: Counter Access Ports Register
Slave PIC ICW1 Init. Cmd Word 1 A4h, A8h, Undefined Register ACh, B0h, Slave PIC OCW2 Op Ctrl Word 2 Register 001XXXXXb B4h, B8h, Slave PIC OCW3 Op Ctrl Word 3 Register X01XXX10b ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 361: Icw1-Initialization Command Word 1 Register
Edge/Level Bank Select Disabled. Replaced by the edge/level triggered control (LTIM) registers (ELCR). ® 0 = Ignored for the Intel 6300ESB ICH. Should be programmed to 0. Single or Cascade 0 = Must be programmed to a 0 to indicate two controllers (SNGL) operating in cascade mode.
Page 362: Icw2-Initialization Command Word 2 Register
INTA# cycle. The code is a three bit binary code: Code Master InterruptSlave Interrupt Interrupt Request Level IRQ0 IRQ8 IRQ1 IRQ9 IRQ2 IRQ10 IRQ3 IRQ11 IRQ4 IRQ12 IRQ5 IRQ13 IRQ6 IRQ14 IRQ7 IRQ15 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 363: Icw3-Master Controller Initialization Command Word 3 Register
02h to match the code broadcast by the master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 364: Icw4-Initialization Command Word 4 Register
0 = Should normally be disabled by writing a 0 to this bit. Mode (SFNM) 1 = Special fully nested mode is programmed. ® 0 = Must be programmed to 0 for the Intel 6300ESB ICH. Buffered Mode (BUF) This is non-buffered mode.
Page 365: Ocw2-Operational Control Word 2 Register
L2, L1 and L0 to 0 is sufficient in this case. Interrupt Level Select Bits Interrupt LevelBitsInterrupt Level (L2, L1, L0) IRQ0/8 IRQ4/12 IRQ1/9 IRQ5/13 IRQ2/10 IRQ6/14 IRQ3/11 IRQ7/15 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 366: Ocw3-Operational Control Word 3 Register
OCW3 must be reprogrammed prior to attempting the read. 00 = No Action 01 = No Action 10 = Read IRQ Register 11 = Read IS Register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 367: Elcr1-Master Controller Edge/Level Triggered Register
0 = Edge. IRQ15 ECL 1 = Level. 0 = Edge. IRQ14 ECL 1 = Level. Reserved Reserved. Must be 0. 0 = Edge. IRQ12 ECL 1 = Level. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 368: Advanced Interrupt Controller (Apic0)
FEC0_0020H or FEC1_0020H) to generate interrupts from APIC1. ® Since the Intel 6300ESB ICH does not implement Hub Interface EOI special cycle, the MCH will translate EOI special cycle to a memory write cycle to EOI register at address ®...
Page 369: Apic Indirect Registers
This is a 32-bit register specifying the data to be read or written to the register pointed to by the Index register. This register may only be accessed in DWORD quantities. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 370: Dat-Data Register
PCI devices will use this field. ® Note: Writes to this register are only allowed by the processor and by masters on the Intel ® 6300ESB ICH’s PCI bus. Writes by devices on PCI buses above the Intel 6300ESB ICH are not supported.
Page 371: Offset 00H: Id-Identification Register
Size: Bits Name Description Access 31:2 Reserved Reserved. 27:2 APIC ID Software must program this value before using the APIC. 23:1 Reserved Reserved. Scratchpad Scratchpad bit. 14:0 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 372: Offset 01H: Ver-Version Register
Reserved Reserved. This is a version number that identifies the implementation ® Version version. The version number assigned to the Intel 6300ESB ICH for the I/O (x) APIC is 20h. 8.5.8 Offset 02h: ARBID—Arbitration ID Register Note: This register contains the bus arbitration priority for the APIC. When the APIC Clock is running, this register is loaded whenever the APIC ID register is loaded.
Page 373: Offset 10H - 11H (Vector 0) Through 3E - 3Fh (Vector 23): Redirection Table
These bits are only sent to a local APIC when in Processor (EDID) System Bus mode. They become bits [11:4] of the address. 47:1 Reserved Reserved. Software should program these bits to 0 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 374 These encodings are listed in the note below: This field contains the interrupt vector for this interrupt. Vector Values range between 10h and FEh. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 375: Real Time Clock Registers
RAM. All data movement between the host processor and the real-time clock is done through registers mapped to the standard I/O space. The register map appears in Table 260. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 376: Indexed Registers
Minutes Alarm Hours Hours Alarm Day of Week Day of Month Month Year Register A Register B Register C Register D 0Eh - 7Fh 114 Bytes of User RAM ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 377: Rtc_Regd-Register D (Flag Register)
8.6.2.1 RTC_REGA—Register A Note: This register is used for general configuration of the RTC functions. None of the bits are ® affected by RSMRST# or any other Intel 6300ESB ICH reset signal. Table 262. RTC_REGD—Register D (Flag Register) Device: Function:...
Page 378: Rtc_Regb-Register B (General Configuration)
Interrupt Enable 1 = Allows an interrupt to occur when the update cycle ends. ® This bit serves no function in the Intel 6300ESB ICH. It is left in this register bank to provide compatibility with the SQWE: Square Wave ®...
Page 379 1:59:59 AM, it is changed to 1:00:00 AM. The time must increment normally for at least two update cycles (seconds) previous to these conditions for the time change to occur properly. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 380: Rtc_Regc-Register C (Flag Register)
When the date alarm is not enabled, these bits will return zeros to mimic the functionality of the Motorola 146818B. These bits are not affected by RESET. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 381: Nmi_Sc-Nmi Status And Control Register
0 = SPKR output is a 0. SPKR_DAT_EN: Speaker 1 = SPKR output is equivalent to the Counter 2 OUT signal Data Enable value. TIM_CNT2_EN: Timer 0 = Disable Counter 2 Enable 1 = Enable ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 382: Nmi_En-Nmi Enable (And Real Time Clock Index)
0 = A20M# signal may potentially go active. 1 = This bit is set when INIT# goes active. ® When this bit transitions from a 0 to a 1, the Intel 6300ESB INIT_NOW ICH will force INIT# active for 16 PCI clocks.
Page 383: Coproc_Err-Coprocessor Error Register
This bit is used to determine a hard or soft reset to the processor. ® 0 = When RST_CPU bit goes from 0 to 1, the Intel 6300ESB ICH performs a soft reset by activating INIT# for 16 PCI clocks.
Page 384: Power Management Pci Configuration Registers
00000000 B8 - BBh GPI_ROUT GPI Route Control MON_FWD_EN I/O Monitor Forward Enable C4 - CAhh MON[n]_TRP_RNG I/O Monitor[4:7] Trap Range 0000h MON_TRP_MSK I/O Monitor Trap Range Mask 0000h ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 385: Offset A0H: Gen_Pmcon_1-General Pm Configuration 1 Register (Pm-D31:F0)
Set by software to control the rate at which periodic SMI# is generated. 00 = 64 seconds PER_SMI_SEL: Periodic SMI# rate Select 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 386: Offset A2H: Gen_Pmcon_2-General Pm Configuration 2 Register (Pm-D31:F0)
Reserved. ® The Intel 6300ESB ICH sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit and clear System Reset Status it when it is set. This bit is also reset by RSMRST# and CF9h...
Page 387: Offset A4H: Gen_Pmcon_3-General Pm Configuration 3 Register (Pm-D31:F0)
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period ® may not be detected by the Intel 6300ESB ICH. ® Intel...
Page 388: Offset Ach: Rst_Cnt2-Reset Control 2 Register (Pm-D31:F0)
Reset Enable 0 = CF9h write of 6h or Eh will reset resume well logic, This field selects the handling of CPUTHRMTRIP# event by the ® Intel 6300ESB ICH internal logic. Bits CPUTHRMTRIP# Behavior CPUTHRMTRIP# Event will cause asynchronous assertion of...
Page 389: Offset B8H - Bbh: Gpi_Rout-Gpi Routing Control Register (Pm-D31:F0)
GPIs will not cause wake events, 00 = No effect. 01 = SMI# (when corresponding ALT_GP_SMI_EN bit is also set) 10 = SCI (when corresponding GPE0_EN bit is also set) 11 = Reserved ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 390: Offset C0H: Mon_Fwd_En-Io Monitor Forward Enable Register (Pm-D31:F0)
® Note: The Intel 6300ESB ICH uses this register to enable the monitors to forward cycles to LPC, independent of the POS_DEC_EN bit and the bits that enable the monitor to generate an SMI#. The only criteria is that the address passes the decoding logic as determined by the MON[n]_TRP_RNG and MON_TRP_MSK register settings.
Page 391: Offset C4H, C6H, C8H, Cah: Mon[N]_Trp_Rng-I/O Monitor [4:7] Trap Range Register For Devices 4-7 (Pm-D31:F0)
6300ESB ICH component). When the cycle is to be claimed by the Intel 6300ESB ICH and the intended target is on LPC, an SMI# will be generated but the cycle will only be forwarded to the intended target when forwarding to LPC is enabled through the TRP_FWD_EN register settings.
Page 392: Apm_Cnt-Advanced Power Management Control Port Register
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is not affected by any other register or function (other than a PCI reset). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 393: Power Management I/O Registers
Device Monitor SMI Status 0000h and Enable Device Activity Status 0000h Device Trap Enable Register 0000h 4Ch-4Dh Bus Address Tracker Last Cycle Bus Cycle Tracker Last Cycle 60h-7Fh Reserved for TCO Registers ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 394: Pm1_Sts-Power Management 1 Status Register
6300ESB ICH will generate a Wake Event. Once back in an ® S0 state (or if already in an S0 state when the event occurs), the Intel 6300ESB ICH will also generate an SCI when the SCI_EN bit is set, or an SMI# when the SCI_EN bit is not set.
Page 395 Overflow Status every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 396: Pm1_En-Power Management 1 Enable Register
SMI# If system was in S1-S5, then a Enable wake vent occurs before the SMI# SCI If system was in S1-S5, then a wake vent occurs before the SMI# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 397: Pm1_Cnt-Power Management 1 Control
PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS. SCI_EN: SCI Enable 0 = These events will generate an SMI#. 1 = These events will generate an SCI. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 398: Pm1_Tmr-Power Management 1 Timer Register
FORCE_THTL: Force 0 = No forced throttling. Thermal Throttling 1 = Throttling at the duty cycle specified in THRM_DTY starts immediately (no 2 second delay), and no SMI# is generated. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 399 STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs. THRM_DTY Throttle ModePCI Clocks 50% Default THTL_DTY 87.5% 75.0% 62.5% 37.5% 12.5% Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 400: Lv2-Level 2 Register
Note: This register is symmetrical to the General Purpose Event 0 Enable Register. When the ® corresponding _EN bit is set, and the _STS bit get set, the Intel 6300ESB ICH will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the ®...
Page 401: Gpe0_Sts—General Purpose Event 0 Status Register
15:1 Reserved Reserved. ® This bit will be set to 1 by the Intel 6300ESB ICH when any internal device on bus 0 asserts the equivalent of the PME# signal. Additionally, when the PME_B0_EN bit is set, and the system is in an S0 state, the setting of the PME_B0_STS bit will generate an SCI (or SMI# when SCI_EN is not set).
Page 402 1 = Set by hardware to indicate that the wake event was ® caused by the Intel 6300ESB ICH’s SMBus logic.This bit will be set by the WAKE/SMI# command type, even when the system is already awake. The SMI handler should then clear this bit.
Page 403 THRM_POL bit. Additionally, R/WC Status (THRM_STS) when the THRM_EN bit is set, the setting of the THRM_STS bit will also generate a power management event (SCI or SMI#). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 404: Gpe0_En-General Purpose Event 0 Enables Register
1 = Enables the setting of the TCOSCI_STS to generate an SCI. 0 = Disable. AC97_EN 1 = Enables the setting of the AC97_STS to generate a wake event. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 405: Smi_En-Smi Control And Enable Register
Lockable: Power Well: Bits Name Description Access 31:1 Reserved Reserved. INTEL_USB2_EN Enables Intel-Specific USB EHCI SMI logic to cause SMI#. LEGACY_USB2_EN Enables legacy USB EHCI logic to cause SMI#. 16:1 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007...
Page 406 SMI Enable SMI#. Note that “trapped’ cycles will be claimed by the ® Intel 6300ESB ICH on PCI, but not forwarded to LPC. 10:8 Reserved Reserved. 0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
Page 407: 8.8.3.10 Smi_Sts-Smi Status Register
SMI event. 8.8.3.10 SMI_STS—SMI Status Register ® Note: When the corresponding _EN bit is set when the _STS bit is set, the Intel 6300ESB ICH will cause an SMI# (except bits 8-10 and 12, which do not need enable bits since ®...
Page 408 Reserved Reserved. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the Intel-Specific USB EHCI SMI Status Register INTEL_USB2_STS ANDed with the corresponding enable bits. This bit will not be active when the enable bits are not set. Writes to this bit will have no effect.
Page 409 MCSMI_EN bit is also set, the ® Intel 6300ESB ICH will generate an SMI#. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the ALT_GP_SMI_EN register.
Page 410: 8.8.3.11 Alt_Gp_Smi_En-Alternate Gpi Smi Enable Register
• The corresponding bit in the ALT_GP_SMI_EN register is 15:0 set. • The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI. • The corresponding GPIO must be implemented. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 411: 8.8.3.12 Alt_Gp_Smi_Sts-Alternate Gpi Smi Status Register
Bit 8 corresponds to Monitor 4, bit 9 corresponds to Monitor 5 etc. 11:8 DEV[7:4]_TRAP_EN 0 = Disable. 1 = Enables SMI# due to an access to the corresponding device monitor’s I/O range. Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 412: 8.8.3.14 Devact_Sts-Device Activity Status Register
0 = The corresponding PCI interrupts have not been active. PIRQDH_ACT_STS R/WC 1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by writing a 1 to the bit location. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 413 0 = Indicates that there has been no access to this device’s I/ IDEP0_ACT_STS R/WC O range. 1 = This device’s I/O range has been accessed. Clear this bit by writing a 1 to the bit location. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 414: 8.8.3.15 Devtrap_En- Device Trap Enable Register
Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk Controller. LEG_IO_TRP_EN 0 = Disable. 1 = Enable. Reserved Reserved. IDE Secondary Drive 1. IDES1_TRP_EN 0 = Disable. 1 = Enable. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 415: 8.8.3.16 Bus_Addr_Track- Bus Address Tracker
Asynchronous SMIs and Synchronous SMIs are occurring simultaneously. This register only reports “expected” last I/O cycle data when Asynchronous SMIs are disabled. Note: Usage: Legacy only. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 416: System Management Tco Registers (D31:F0)
TCO2_STS: TCO Status 08h - 09h TCO1_CNT: TCO Control 0Ah - 0Bh TCO2_CNT: TCO Control TCO_MESSAGE1, TCO_MESSAGE2: Used by BIOS to indicate POST/Boot 0Ch - 0Dh progress TCO_WDSTATUS: Watchdog Status Register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 417: Tco1_Rld-Tco Timer Reload And Current Value
Values of 0h - 3h will be ignored and should not be attempted. The timer is clocked at approximately 0.6 seconds, and this allows timeouts ranging from 2.4 seconds to 38 seconds. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 418: Tco1_Dat_In-Tco Data In Register
Data Register for passing commands from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL bits. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 419: Tco1_Sts-Tco1 Status Register
(D30:F0, Offset 04h, bit 8) is also set, the ® Intel 6300ESB ICH will set the SSE bit in SECSTS register (D30:F0, offset 1Eh, bit 14) AND will also generate a NMI (or SMI# when NMI routed to SMI#).
Page 420 0 = Software clears this bit by writing a 1 to the bit position. ® TIMEOUT 1 = Set by the Intel 6300ESB ICH to indicate that the SMI R/WC was caused by the TCO timer reaching 0. 0 = Software clears this bit by writing a 1 to the bit position.
Page 421: Tco2_Sts-Tco2 Status Register
This bit is set by the Intel 6300ESB ICH when it detects FFh ® on the first BIOS read (i.e., the BIOS is bad). Intel 6300ESB ICH clears this bit to 0 if the first BIOS read is not FFh. This is detected when the initial read returns FFh from the FWH.
Page 422: Tco1_Cnt-Tco1 Control Register
6300ESB ICH has set it SEND_NOW back to 0. ® 1 = Writing a 1 to this bit will cause the Intel 6300ESB ICH to send an Event message with the Software Event bit set. 0 = Normal NMI functionality.
Page 423: Tco2_Cnt-Tco2 Control Register
TCO_MESSAGE[n] system management software to indicate more details on the boot progress. This register will be reset to the default of 00h based on RSMRST# (but not PCI reset). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 424: Offset Tcobase + Oeh: Tco_Wdstatus-Tco2 Control Register
6300ESB ICH’s SERIRQ logic. This IRQ12_CAUSE ® bit must be a ‘1’ (default) when the Intel 6300ESB ICH is expected to receive IRQ12 assertions from a SERIRQ device. The state of this bit is logically ANDed with the IRQ1 signal as ®...
Page 425: General Purpose I/O Registers (D31:F0)
2C-2Fh GPI_INV GPIO Signal Invert 00000000h GPIO_USE_SEL 30-33h GPIO Use Select 03000000h 34-37h GP_IO_SEL2 GPIO Input/Output Select 2 00000000h 38-3Bh GP_LVL2 GPIO Level for Input or Output 2 00000FFFh ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 426: Offset Gpiobase + 00H: Gpio_Use_Sel-Gpio Use Select Register
0 = Output. The corresponding GPIO signal is an output. GPIO[n]_SEL 25:2 1 = Input. The corresponding GPIO signal is an input. Always 0. The GPIOs are fixed as outputs. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 427: Offset Gpiobase + 0Ch: Gp_Lvl-Gpio Level For Input Or Output Register
Resume well, and will be reset to their default values by RSMRST# and also by a write to the CF9h register. 0 = Low 1 = High ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 428 1 = High Reserved. These bits are not needed as the level of general inputs can be read through the GPE0_STS and 15:0 Reserved ALT_GP_SMI_STS registers. See Section 8.8.3.7 Section 8.8.3.12 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 429: Offset Gpiobase + 18H: Gpo_Blink-Gpo Blink Enable Register
The high and low times are approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is set. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 430: Offset Gpiobase + 2Ch: Gpi_Inv-Gpio Signal Invert Register
1, 8 0 = The corresponding GPIn_STS bit will be set when the ® Intel 6300ESB ICH detects the state of the input pin to be high. 1 = The corresponding GPIn_STS bit will be set when the ® Intel 6300ESB ICH detects the state of the input pin to be low.
Page 431: Offset Gpiobase + 30H:gpio_Use_Sel2-Gpio Use Select 2 Register
GPIO. After just a PXPCIRST#, the GPIO in the core well are configured as GPIO. Implementation Note: Bits 26:31 may be in CORE Well. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 432: Offset Gpiobase + 38H: Gp_Lvl2-Gpio Level For Input Or Output 2 Register
‘1’ but allows for an external pullup to GP_LVL[57:56] cause a high value on the pin. Since these bits correspond to GPIO that are in the RTC well, these bits will be reset by RTCRST#. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 433 (1 = high, 0 = low). Writes will have no effect. Since these bits correspond to GPIO that are in the core well, these bits will be reset by PXPCIRST#. Implementation Note: Bits 26:31 may be in CORE Well. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 434 ® Intel 6300ESB ICH—8 This page intentionally left blank. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 435: Pci Configuration Map (Ide-D31:F1)
6300ESB ICH Specification Update for the most up-to-date value of the Revision ID Register. ® 2. The Intel 6300ESB ICH IDE controller is not arbitrated as a PCI device, therefore it does not need a master latency timer. ® Intel...
Page 436: Offset 00 - 01H: Vid-Vendor Id Register (Lpc I/F-D31:F1)
Description Access 15:0 Vendor ID Value This is a 16-bit value assigned to Intel. Intel VID = 8086h. 9.1.2 Offset 02 - 03h: DID—Device ID Register (LPC I/ F—D31:F1) Table 324. Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1)
Page 437: Offset 04H - 05H: Cmd-Command Register (Ide-D31:F1)
Reserved as ‘0’. (SCE) ® Bus Master Enable Controls the Intel 6300ESB ICH’s ability to act as a PCI (BME) master for IDE Bus Master transfers. 0 = Disables access. 1 = Enables access to the IDE Expansion memory range. The...
Page 438: Offset 06 - 07H: Sts-Device Status Register (Ide-D31:F1)
Reserved Reserved as ‘0’. 0 = Cleared by writing a 1 to it. ® Signaled Target-Abort 1 = The Intel 6300ESB ICH IDE interface function is R/WC ® Status (STA) targeted with a transaction that the Intel 6300ESB ICH terminates with a target abort.
Page 439: Offset 08H: Rid-Revision Id Register (Ide-D31:F1)
Size: Bits Name Description Access ® This read-only bit is a 1 to indicate that the Intel 6300ESB ICH supports bus master operation Reserved Reserved. Will always return 0. This read-only bit is a 1 to indicate that the secondary SOP_MODE_CAP controller supports both legacy and native modes.
Page 440: Offset 0Ah: Scc-Sub Class Code (Ide-D31:F1)
Table 329. Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1) Device: Function: Read-Only Offset: Attribute: 8-bit Default Value: Size: Bits Name Description Access Sub Class Code 01h = IDE device, in the context of a mass storage device. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 441: Offset 0Bh: Bcc-Base Class Code (Ide-D31:F1)
This bit is set to one, indicating a request for IO space. Read- (RTE) Only. NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 442: Offset 14H - 17H: Pcnl_Bar-Primary Control Block Base Address Register (Ide-D31:F1)
This bit is set to one, indicating a request for IO space. (RTE) NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 443: Offset 1Ch - 1Fh: Scnl_Bar-Secondary Control Block Base Address Register (Ide D31:F1)
Reserved Reserved. 15:4 Base Address Base address of the I/O space (16 consecutive I/O locations). Reserved Reserved. Resource Type Indicator Hardwired to’1’, indicating a request for IO space. (RTE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 444: Offset 24H - 27H: Cpba - Ide Command Posting Base Address
® Note: The Intel 6300ESB ICH requests 1 Kbyte of memory space for the Command Posting accesses. This is much more than is needed; by requesting this much space, decoding may be simplified. In addition to the standard PCI Memory Space Enable bit, the Command Posting Enable bits in the IDE I/O Configuration register must be set for the ®...
Page 445: Offset 2Ch - 2Dh: Ide_Svid-Subsystem Vendor Id (Ide-D31:F1)
NOTE: Write accesses to the SVID register should only be done as 16-bit accesses. If two 8-bit write accesses are done, then the value in the register will not be correct. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 446: Offset 2Eh - 2Fh: Ide_Sid-Subsystem Id (Ide-D31:F1)
Default Value: Size: Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is used to Interrupt Line communicate to software the interrupt line which the interrupt pin is connected to. ® Intel 6300ESB I/O Controller Hub...
Page 447: Offset 3Dh: Intr_Pn-Interrupt Pin Register (Ide-D31:F1)
Reserved. ® The value of 01h indicates to “software” that the Intel 6300ESB ICH will drive INTA#. Note that this is only used in native mode. Also note that the routing to the internal Interrupt Pi interrupt controller does not necessarily relate to the value in this register.
Page 448 0 = Disable. ® (IDE) 1 = Enables the Intel 6300ESB ICH to decode the associated Command Blocks (1F0-1F7h for primary, 170- 177h for secondary) and Control Block (3F6h for primary and 376h for secondary). This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
Page 449 1 = Enable Prefetch and posting to the IDE data port for this Enable (PPE1) drive. Drive 1 IORDY Sample 0 = Disable IORDY sampling for this drive. Point Enable (IE1) 1 = Enable IORDY sampling for this drive. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 450 Drive 0 Fast Timing Bank this drive. (TIME0) 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 451: Offset 44H: Slv_Idetim-Slave (Drive 1) Ide Timing Register (Ide-D31:F1)
IDE timing register for primary is set. Primary Drive 1 00 = 4 clocks Recovery Time (PRCT1) 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 452: Offset 48H: Sdma_Cnt-Synchronous Dma Control Register (Ide-D31:F1)
1 = Enable Synchronous DMA mode for primary channel drive Enable (PSDE1) Primary Drive 0 0 = Disable (default) Synchronous DMA Mode 1 = Enable Synchronous DMA mode for primary channel drive Enable (PSDE0) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 453: Offset 4A - 4Bh: Sdma_Tim-Synchronous Dma Timing Register (Ide-D31:F1)
10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_SCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 454 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_PCB1 = 1 (133 MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 455: Ide_Config-Ide I/O Configuration Register (Ide-D31:F1)
Status Register Primary R/WC Reserved 04-07 BMIDP Descriptor Table Pointer Primary xxxxxxxxh BMICS Command Register Secondary Reserved BMISS Status Register Secondary R/WC Reserved 0C-0F BMIDS Descriptor Table Pointer Secondary xxxxxxxxh ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 456: Bmic[P,S]-Bus Master Ide Command Register
Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 457: Bmis[P,S]-Bus Master Ide Status Register
Access ® The Intel 6300ESB ICH sets this bit when it completes execution of a PRD that has its PRD_INT bit set. This bit is cleared by software writing a 1 to this bit position. When this bit is cleared, the interrupt is cleared. Note that there is a ®...
Page 458 It is also cleared by ® the Intel 6300ESB ICH when the Start bit is cleared in Bus Master IDE Active the Command register. When this bit is read as a zero, all...
Page 459: Bmid[P,S]-Bus Master Ide Descriptor Table Pointer Register
Note: When this register is read, the current value of the pointer is returned. The Intel 6300ESB ICH does NOT return the original base value of the pointer once one or more descriptors have been executed. This capability is useful for enabling low-cost disk drives.
Page 460 ® Intel 6300ESB ICH—9 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 461: Usb Uhci Controllers Registers
2000h Mouse Control USB_RES USB Resume Enable ® NOTE: Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to- date value of the Revision ID Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 462: Offset 00 - 01H: Vid-Vendor Identification Register (Usb-D29:F0/F1)
16-bit Default Value: Size: Function 1: 25AAh Bits Name Description Access ® This is a 16-bit value assigned to the Intel 6300ESB ICH 15:0 Device ID Value USB Host Controllers. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 463: Offset 04 - 05H: Cmd-Command Register (Usb-D29:F0/F1)
Special Cycle Enable Reserved as ‘0’. (SCE) ® Bus Master Enable When set, the Intel 6300ESB ICH may act as a master on (BME) the PCI bus for USB transfers. Memory Space Enable Reserved as ‘0’. (MSE) This bit controls access to the I/O space registers.
Page 464: Offset 06 - 07H: Sta-Device Status Register (Usb-D29:F0/F1)
1 = USB function is targeted with a transaction that the R/WC Status (STA) ® Intel 6300ESB ICH terminates with a target abort. This 2-bit field defines the timing for DEVSEL# assertion. ® These read only bits indicate the Intel 6300ESB ICH's...
Page 465: Offset 09H: Pi-Programming Interface (Usb-D29:F0/F1)
Note: Since the USB controller is internally implemented with arbitration through the Hub Interface, not PCI, it does not need a master latency timer. The bits are fixed at ‘0’. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 466: Offset 0Eh: Htype-Header Type Register (Usb-D29:F0/F1)
Device 31, Function 0, Offset F2h as follows: Multi-Function Bit D29:F0 D29:F1 Multi-Function (Bit 15) (Bit 9) Hardwired to 00h, which indicates the standard PCI Configuration Layout configuration layout. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 467: Offset 20 - 23H: Base-Base Address Register (Usb-D29:F0/F1)
15:0 distinguish subsystems from each other. The value returned (SVID) by reads to this register is the same as that which was written by BIOS into the IDE_SVID register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 468: Offset 2Eh-2Fh: Sid-Subsystem Id (Usb-D29:F0/F1)
Default Value: Size: Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is to Interrupt Line communicate to software the interrupt line that the interrupt pin is connected to. ® Intel 6300ESB I/O Controller Hub...
Page 469: Offset 3Dh: Intr_Pn-Interrupt Pin Register (Usb-D29:F0/F1)
Interrupt Pin ® Note that this does not determine the mapping to the Intel 6300ESB ICH PIRQ inputs. Function 0 will drive PIRQA. Function 1 will drive PIRQD. Function 1 does not use the corresponding mapping in order to spread the interrupts with AC’97, which has historically been mapped to PIRQB...
Page 470 NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set. Section 8.1.37, “Offset F4: ETR1—PCI-X Extended Features Register (LPC I/F—D31:F0)” more information. Port 64 Reads initiated from an external PCI agent will not set this bit. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 471 SMI on Port 64 Writes Section 8.1.37, “Offset F4: ETR1—PCI-X Enable (64WEN) Extended Features Register (LPC I/F—D31:F0)” more information. Port 64 Writes initiated from an external PCI agent will not set this bit. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 472: Offset C4H: Usb_Res-Usb Resume Enable Register (Usb-D29:F0/F1)
0 = The USB controller will not look at this port for a wakeup event. PORT0EN 1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 473: Usb I/O Registers
Writing to the register causes a command to be executed. The table following the bit description provides additional information on the operation of the Run/Stop and Debug bits. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 474 0 = Disable loop back test mode. ® 1 = The Intel 6300ESB ICH is in loop back test mode. When Loop Back Test Mode both ports are connected together, a write to one port will be seen on the other port, and the data will be stored in I/O offset 18h.
Page 475 The Host Controller is able to receive resume signals from USB and interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared prior to setting this bit. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 476 When this bit is cleared, ® the Intel 6300ESB ICH completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state.
Page 477: Run/Stop, Debug Bit Interaction Swdbg (Bit 5), Run/Stop (Bit 0) Operation
This HCHalted bit may also be used outside of Software Debug mode to indicate when the Host Controller has detected the Run/Stop bit and has completed the current transaction. Outside of the Software Debug mode, setting the Run/Stop bit to ’0’ ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 478: Offset 02 - 03H: Usbsta-Usb Status Register
PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the system. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 479: Offset Base + (04 - 05H): Usbintr-Interrupt Enable Register
Base + (04-05h) Read/Write Offset: Attribute: 0000h 16-bit Default Value: Size: Bits Name Description Access 15:5 Reserved Reserved. Scratchpad Scratchpad. Short Packet Interrupt 0 = Disabled. Enable 1 = Enabled. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 480 Interrupt On Complete 0 = Disabled. (IOC) Enable 1 = Enabled. Resume Interrupt 0 = Disabled. Enable 1 = Enabled. Timeout/CRC Interrupt 0 = Disabled. Enable 1 = Enabled. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 481: Offset Base + (06 - 07H): Frnum-Frame Number Register
Base + (08-0Bh) Read/Write Offset: Attribute: Undefined 32-bit Default Value: Size: Bits Name Description Access 31:1 These bits correspond to memory address signals [31:12], Base Address respectively. 11:0 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 482: Offset Base + Och: Sofmod-Start Of Frame Modify Register
Timing Value to program into this field for a certain frame period. Frame Length (# 12 MHz Clocks) SOF Reg. Value SOF Timing Value (decimal) (decimal) 11936 11937 11999 12000 12001 12062 12063 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 483: Portsc[0,1]-Port Status And Control Register
10.2.7 PORTSC[0,1]—Port Status and Control Register ® Note: For Function 0 this applies to the Intel 6300ESB ICH USB ports 0 and 1; for Function ® 1 this applies to the Intel 6300ESB ICH USB ports 2 and 3. After a Power-up reset, Global reset, or Host Controller reset, the initial conditions of a port are: no device connected, Port disabled, and the bus line status is 00 (single- ended ‘0’).
Page 484 32 microseconds while the port is in the ® Suspend state. The Intel 6300ESB ICH will then reflect the K-state back onto the bus as long as the bit remains a ‘1’ and Resume Detect the port is still in the suspend state (bit 12, 2 are ‘11’).
Page 485: Usb Ehci Configuration Registers (D29:F7)
62-63h Power Wake Capabilities 007Fh 64-65h Classic USB Override 0000 NOTE: Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up- to-date value of the Revision ID Register. ® Intel 6300ESB I/O Controller Hub November 2007...
Page 486: Offset 04 - 05H: Command Register
HS_ Ref_V_USB HS Reference 00000000h Read/Write Voltage Register NOTE: Refer to the Intel® 6300ESB I/O Controller Hub Specification Update for the most up- to-date value of the Revision ID Register. 11.1.1 Offset 04 - 05h: Command Register Table 379. Offset 04 - 05h: Command Register...
Page 487: Offset 06 - 07H: Device Status
0 = Software clears this bit by writing a ’1’ to this bit location. ® Signaled System Error 1 = This bit is set by the Intel 6300ESB ICH whenever it (SSE) signals SERR# (internally). The SER_EN bit (bit 8 of the Command Register) must be ’1’...
Page 488 ® Intel 6300ESB ICH—11 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 489: Offset 08H: Rid-Revision Id Register
Size: Bits Name Description Access ® Refer to the Intel 6300ESB I/O Controller Hub Specification Revision ID Value Update for the most up-to-date value of the Revision ID Register. 11.1.4 Offset 09h: Programming Interface Table 382. Offset 09h: Programming Interface...
Page 490: Offset 0Bh: Base Class Code
32-bit address space. Resource Type Indicator This field is hardwired to 00b indicating that this range may (RTE) be mapped anywhere within 32-bit address space. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 491: Offset 2C - 2Dh: Usb Ehci Subsystem Vendor Id
Table 389. Offset 34h: Capabilities Pointer Device: Function: Read-Only Offset: Attribute: 8-bit Default Value: Size: Bits Name Description Access This register points to the starting offset of the USB EHCI Capabilities Pointer capabilities ranges. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 492: 11.1.12 Offset 3Ch: Interrupt Line
Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is used as Interrupt Line a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to. 11.1.13 Offset 3Dh: Interrupt Pin Table 391.
Page 493: 11.1.15 Offset 51H: Next Item Pointer #1
D1 or D2 states. For all other states, the RW-Special ® Intel 6300ESB ICH EHC is capable of generating PME#. Software should never need to modify this field. D2_Support Hardwired to 0 = D2 State is not supported.
Page 494: Offset 54 - 55H: Power Management Control/Status
1. Normally, this register is read-only to report capabilities to the power management software. To report ® different power management capabilities depending on the system in which the Intel 6300ESB ICH is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit is set. The value written to this register does not affect the hardware other than changing the value returned during a read.
Page 495: 11.1.18 Offset 58H: Debug Port Capability Id
When not in the D0 state, the generation of the interrupt output is blocked. ® Specifically, the PIRQ[H] is not asserted by the Intel 6300ESB ICH when not in the D0 state. When software changes this value from the D3hot state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function.
Page 496: 11.1.19 Offset 59H: Next Item Pointer #2
HChalted bit in the USBSTS register is a ‘1’. Changing value of this register while the host controller is operating yields undefined results. It ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 497: 11.1.23 Offset 62 - 63H: Port Wake Capability
BIOS initializing this register to a system-specific value. System software uses the information in this register when enabling devices and ports for remote wake-up. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 498: Offset 64 - 65H: Classic Usb Override
EHCI port routing logic. The corresponding EHCI port will always appear disconnected in this mode. Note: EHCI test modes will not work on a port that has been overridden by this register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 499: Offset 68 - 6Bh: Usb Ehci Legacy Support Extended Capability
A value of 00h indicates that there are no EHCI Extended 15:8 Capability Capability structures in this device. Pointer Capability A value of 01h indicates that this EHCI Extended Capability is the Legacy Support Capability. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 500: Offset 6C - 6Fh: Usb Ehci Legacy Support Extended Control/Status
SMI on Async Advance When this bit is a ’1’ and the SMI on Async Advance bit is a Enable ’1’, the host controller will issue an SMI immediately. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 501: 11.1.27 Offset 70 - 73H: Intel Specific Usb Ehci Smi
(R/WC). Software should clear all SMI status bits prior to setting the global SMI enable bit and individual SMI enable bit to prevent spurious SMI when returning from a powerdown. Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 1 of 2) Device: Function:...
Page 502 ® Intel 6300ESB ICH—11 Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 2 of 2) Device: Function: 70-73h Read/Write Offset: Attribute: 00000000h 32-bit Default Value: Size: Suspend Power Well: Bits Name Description Access This bit is set to ‘1’ whenever the Periodic Schedule Enable bit...
Page 503: 11.1.28 Offset 80H: Access Control
Reserved Reserved NOTE: System BIOS should program a value of '111111b' into D29:F7:Register Offset DCh, bits 21:16 during POST and resume from S3(STR)/S4(STD) states on ALL steppings of the Intel 6300ESB ICH. 11.2 Memory-Mapped I/O Registers The USB 2.0 EHCI memory-mapped I/O space is composed of two sets of registers: Capability Registers and Operational Registers.
Page 504: 11.2.1.1 Offset 00H: Caplength-Capability Registers Length
This register is used as an offset to add to the Memory Base Register to find the beginning of the Operational Register Space. This is fixed at 20h, indicating that the Operation Registers begin at offset 20h. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 505: Offset 02 - 03H: Hciversion-Host Controller Interface Version Number
31:2 Reserved Reserved. Default = 0h. 23:2 Debug Port Number Hardwired to 1h, indicating that the Debug Port is on the ® (DP_N) lowest numbered port on the Intel 6300ESB ICH. 19:1 Reserved Reserved. Reserved Reserved. Hardwired to 0. ®...
Page 506 Controllers (N_CC) are supported on the host controller root ports. ® The Intel 6300ESB ICH allows the default value of 2h to be ® over-written by BIOS. Since the Intel 6300ESB ICH cannot support more than two companion host controllers, bits 15:14 are implemented as read-only 00b.
Page 507: Offset 08 - 0Bh: Hccparams-Host Controller Capability Parameters
Values for this field have the following interpretation: Capability 0 = Data structures using 32-bit address memory pointers 1 = Data structures using 64-bit address memory pointers This bit is hardwired to 1. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 508 Suspend power well. Unless otherwise noted, the suspend-well registers are reset by the assertion of either of the following: • Suspend well hardware reset • HCRESET ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 509: Offset Caplength + 00 - 03H: Usb Ehci Cmd-Usb Ehci Command Register
Mode Bits ® Light Host Controller The Intel 6300ESB ICH does not implement this optional Reset reset and hardwires this bit to 0. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.
Page 510 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. ® The Intel 6300ESB ICH hardwires this field to 00b because it Frame List Size only supports the 1024-element frame list size. ® Intel...
Page 511 The effects of this on Root Hub registers are similar to a Chip Hardware Reset (i.e., RSMRST# assertion and ® PWROK deassertion on the Intel 6300ESB ICH). When software writes a ’1’ to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc.
Page 512: Offset Caplength + 04 - 07H: Usb Ehci Sts-Usb Ehci Status
’1’ to the Interrupt on R/WC Advance Async Advance Doorbell bit in the USBCMD register. This bit indicates the assertion of that interrupt source. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 513 Index rolls over from its maximum value to ’0’. Since the ® Frame List Rollover Intel 6300ESB ICH only supports the 1024-entry Frame List R/WC Size, the Frame List Index rolls over every time FRNUM[13] toggles. The Host Controller sets this bit to a ’1’ when any port for which the Port Owner bit is set to ’0’...
Page 514: Offset Caplength + 08 - 0Bh: Usb Ehci Intr-Usb Ehci Interrupt Enable
Periodic Frame List during periodic schedule ® execution. The number of bits used for the index is fixed at 10 for the Intel 6300ESB ICH since it only supports 1024-entry frame lists. This register must be written as a ®...
Page 515: Offset Caplength + 10 - 13H: Ctrldssegment-Control Data Structure Segment Register
® EHCI data structures. Since the Intel 6300ESB ICH hardwires the 64-bit Addressing Capability field in HCCPARAMS to ‘1’, then this register is used with the link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address.
Page 516: Offset Caplength + 14 - 17H: Periodiclistbase-Periodic Frame List Base Address
® executed. Since the Intel 6300ESB ICH host controller operates in 64-bit mode (as indicated by a ‘1’ in 64-bit Addressing Capability field in the HCCPARAMS register), then the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register.
Page 517: Offset Caplength + 40 - 43H: Configflag-Configure Flag Register
3. When a port is being used as the Debug Port, the port may report device connected and enabled when the Configured Flag is a ’0’. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 518: Portsc- Port N Status And Control
See Section 4 of the EHCI Specification for operational details. Read-only with a value of ‘1’. This indicates that the port does Port Power (PP) have power. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 519 HCHalted bit is a ’1’. This field is ’0’ if Port Power is ’0’. Warning:System software should not attempt to reset a port when the HCHalted bit in the USBSTS register is a ’1’. Doing so will result in undefined behavior. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 520 Over-current Active. Software clears this bit by writing a ’1’ to this bit position. Overcurrent Change R/WC The functionality of this bit is not dependent upon the port owner. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 521 Overcurrent Active over current condition is removed. ® The Intel 6300ESB ICH automatically disables the port when the over-current active bit is ‘1’. 0 = No change in status. This is the default setting. 1 = Port enabled/disabled status has changed.
Page 522: Offset 00H: Control/Status Register
Port Status and Control register (this is enforced by the hardware). Reset default is ’0’. 27:1 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 523 DONE_STS bit. Default is 0. GO_CNT 1 = Causes hardware to perform a read or write request. Writing a ’1’ to this bit when it is already set may result in undefined behavior. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 524 2. To preserve the usage of Reserved bits in the future, software should always write the same value read from the bit until it is defined. Reserved bits will always return ’0’ when read. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 525: 11.2.3.2 Offset 04H: Usb Pids Register
DATA_LENGTH_CNT field indicates the number of bytes that are valid. NOTE: This register may be accessed as eight separate 8-bit registers or two separate 32-bit registers. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 526: 11.2.3.4 Offset 10H: Config Register
Reserved. This 4-bit field identifies the endpoint used by the controller USB_ENDPOINT_CNF for all Token PID generation. This is a R/W field that is set to 01h after reset. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 527: Offset 00 - 01H: Vid-Vendor Identification Register (Smbus-D31:F3)
Host Configuration NOTES: ® 1. Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the value of the Revision ID Register. 2. Registers that are not shown should be treated as Reserved (See Section 6.2, “PCI for details).
Page 528: Offset 02 - 03H: Did-Device Identification Register (Smbus-D31:F3)
Reserved as ‘0’. (MSE) 0 = Disable I/O Space Enable (IOSE) 1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 529: Offset 06 - 07H: Sta-Device Status Register (Smbus-D31:F3)
Default Value: Size: Bits Name Description Access ® Refer to the Intel 6300ESB I/O Controller Hub Specification Revision ID Value Update for the most up-to-date value of the Revision ID Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 530: Offset 09H: Pi-Programming Interface (Smbus-D31:F3)
Table 432. Offset 0Bh: BCC—Base Class Code Register (SMBUS—D31:F3) Device: Function: Read-Only Offset: Attribute: 8bit Default Value: Size: Bits Name Description Access Base Class Code 0Ch = Serial controller. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 531: Offset 20 - 23H: Smb_Base-Smbus Base Address Register (Smbus-D31:F3)
Name Description Access 31:1 Reserved Reserved. ® Provides the 32-byte system I/O base address for the Intel 15:5 Base Address 6300ESB ICH SMB logic. Reserved Reserved. This read-only bit is always ‘1’, indicating that the SMB logic is IO Space Indicator I/O mapped.
Page 532: Offset 2Eh - 2Fh: Sid-Subsystem Id (Smbus-D31:F2/F4)
Default Value: Size: Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is to Interrupt line communicate to software that the interrupt line is connected to PIRQB#. 12.1.13 Offset 3Dh: INTR_PN—Interrupt Pin Register (SMBUS—D31:F3) Table 437.
Page 533: Offset 40H: Hostc-Host Configuration Register (Smbus-D31:F3)
Reserved Reserved. 0 = SMBus behavior. ® 1 = The Intel 6300ESB ICH is enabled to communicate with C_EN C devices. This will change the formatting of some commands. 0 = SMBus interrupts will not generate an SMI#. 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#.
Page 534: Offset 00H: Hst_Sts-Host Status Register
Note: All status bits are set by hardware and cleared by the software writing a ‘1’ to the particular bit position. Writing a ‘0’ to any bit position has no effect. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 535: Offset 00H: Hst_Sts—Host Status Register
This bit is used as semaphore among various independent ® software threads that may need to use the Intel 6300ESB ICH’s SMBus logic and has no other effect on hardware. 0 = After a full PCI reset, a read to this bit returns a ‘0’.
Page 536 0 = Software resets this bit by writing ’1’ to this location. The ® Intel 6300ESB ICH will then deassert the interrupt or SMI#. 1 = The source of the interrupt or SMI# was the successful completion of its last command.
Page 537: Offset 02H: Hst_Cnt-Host Control Register
1 = Software sets this bit to indicate that the next byte will be the last byte to be received for the block. This causes the ® Intel 6300ESB ICH to send a NACK (instead of an ACK) after receiving the last byte. NOTE: Once the SECOND_TO_STS bit in TCO2_STS register LAST_BYTE (D31:F0, TCOBASE+6h, bit 1) is set, the LAST_BYTE bit also gets set.
Page 538 The bit encoding below indicates which command the Intel ® 6300ESB ICH is to perform. When enabled, the Intel 6300ESB ICH will generate an interrupt or SMI# when the command has completed. When the value is for a non- ®...
Page 539: Offset 03H: Hst_Cmd-Host Command Register
Read/Write Offset: Attribute: 8-bit Default Value: Size: Bits Name Description Access ADDRESS 7-bit address of the targeted slave. Direction of the host transfer. 0 = Write 1 = Read ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 540: Offset 05H: Hst_D0-Data 0 Register
Attribute: 8-bit Default Value: Size: Bits Name Description Access This eight-bit register is transmitted in the DATA1 field of the DATA1 SMBus protocol during the execution of any command. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 541: Offset 07H: Host_Block_Db-Host Block Data Byte Register
Software will then read the data. During the time between when the last byte is read from the SRAM to when the BYTE_DONE_STS bit is cleared, the controller will insert wait states on the interface. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 542: Offset 08H: Pec-Packet Error Check Register
Description Access Reserved Reserved. ® This field is the slave address that the Intel 6300ESB ICH decodes for read and write cycles. The default is not 0, so the SLAVE_ADDR SMBus Slave Interface may respond even before the processor comes up or if the processor is dead. This register is cleared by RSMRST#, but not by PXPCIRST#.
Page 543: Offset 0Ah: Slv_Data-Receive Slave Data Register
CRC Error (CRCE) when a software abort occurs in the middle of the CRC R/WC ® portion of the cycle or an abort happens after the Intel 6300ESB ICH has received the final data bit transmitted by an external slave. ®...
Page 544: 12.2.12 Offset 0Dh: Aux_Ctl-Auxiliary Control Register
Reserved. This Read/Write bit has a default of 1. ® 0 = The Intel 6300ESB ICH will drive the SMLINK[0] pin low, independent of what the other SMLINK logic would SMLINK_CLK_CTL otherwise indicate for the SMLINK[0] pin. 1 = The SMLINK[0] pin is not overdriven low. The other SMLINK logic controls the state of the pin.
Page 545: Offset 0Fh: Smbus_Pin_Ctl-Smbus Pin Control Register
SMBCLK_CTL ® 0 = The Intel 6300ESB ICH will drive the SMBCLK pin low, independent of what the other SMB logic would otherwise indicate for the SMBCLK pin. This read-only bit has a default value that is dependent on an external signal level.
Page 546: 12.2.16 Offset 11H: Slv_Cmd-Slave Command Register
Reserved. ® The Intel 6300ESB ICH sets this bit to a ’1’ when it has completely received a successful Host Notify Command on the SMLink pins. Software reads this bit to determine that the source of the interrupt or SMI# was the reception of the Host Notify Command.
Page 547: Offset 14H: Notify_Daddr-Notify Device Address
This field contains the 7-bit device address received during the Host Notify protocol of the SMBus 2.0 specification. DEVICE_ADDRESS Software should only consider this field valid when the HOST_NOTIFY_STS bit is set to ‘1’. Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 548: Offset 16H: Notify_Dlow-Notify Data Low Byte Register
This field contains the second (high) byte of data received during the Host Notify protocol of the SMBus 2.0 DATA_HIGH_BYTE specification. Software should only consider this field valid when the HOST_NOTIFY_STS bit is set to ‘1’. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 549: Ac'97 Audio Pci Configuration Space (D31:F5)
54-55h Power Management Control and Status 0000h NOTES: ® 1. Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to-date value of the Revision ID Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 550 BIOS programmed registers as BIOS may not be invoked following the D3-to-D0 transition. Resume well registers will not be reset by the D3 to D0 transition. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 551: Offset 00 - 01H: Vid-Vendor Identification Register (Audio-D31:F5)
Power Well: Bits Name Description Access 15:0 Vendor ID Value This is a 16-bit value assigned to Intel. 13.1.2 Offset 02 - 03h: DID—Device Identification Register (Audio—D31:F5) Table 461. Offset 02 - 03h: DID—Device Identification Register (Audio— D31:F5) Device: Function:...
Page 552: Offset 04 - 05H: Pcicmd-Pci Command Register (Audio-D31:F5)
DMA engine halts. Write requests are posted and hence aborts cannot be seen by the ® Intel 6300ESB ICH AC’97 controller for write requests. ® Intel 6300ESB I/O Controller Hub...
Page 553 Data Parity Detected Not implemented. Hardwired to ‘0’. (DPD) ® Fast Back to back Hardwired to ‘1’. This bit indicates that the Intel 6300ESB Capable (FBC) ICH as a target is capable of fast back-to-back transactions. Reserved Reserved. Hardwired to ‘0’.
Page 554: Offset 08H: Rid-Revision Identification Register (Audio-D31:F5)
Power Well: Bits Name Description Access ® Refer to the Intel 6300ESB I/O Controller Hub Specification Revision ID Value Update for the most up-to-date value of the Revision ID Register. 13.1.6 Offset 09h: PI—Programming Interface Register (Audio—D31:F5) Table 465. Offset 09h: PI—Programming Interface Register (Audio—D31:F5)
Page 555: Offset 0Bh: Bcc-Base Class Code Register (Audio-D31:F5)
MMBAR register. This register powers up as read only and only becomes writeable when the IOSE bit in offset 41h is set. For descriptions of these I/O registers, refer to the AC’97 specification. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 556: Offset 14 - 17H: Nabmbar-Native Audio Bus Mastering Base Address Register
These DMA functions are only available from the new MBBAR register. This register powers up as read only and only becomes writeable when the IOSE bit in offset 41h is set. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 557: Offset 18 - 1Bh: Mmbar-Mixer Base Address Register (Audio-D31:F5)
Power Well: Bits Name Description Access Lower 32 bits of the 512-byte memory offset to use for 31:9 Base Address decoding the primary, secondary, and tertiary codec’s mixer spaces. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 558: Offset 1C - 1Fh: Mbbar-Bus Master Base Address Register (Audio-D31:F5)
Reserved. Read as ‘0’s. Type Indicates the base address exists in 32-bit address space. Resource Type Indicator This bit is set to ’0’, indicating a request for memory space. (RTE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 559: Offset 2D - 2Ch: Svid-Subsystem Vendor Id Register (Audio-D31:F5)
Table 474. Offset 2E - 2Fh: SID—Subsystem ID Register (Audio—D31:F5) Device: Function: 2E-2Fh Read/Write Once Offset: Attribute: 0000h 16-bit Default Value: Size: Core Lockable: Power Well: Bits Name Description Access 15:0 Subsystem ID Value R/WO ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 560: Offset 34H: Cap_Ptr-Capabilities Pointer (Audio-D31:F5)
Lockable: Power Well: Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is used to Interrupt Line communicate to software the interrupt line that the interrupt pin is connected to. ® Intel 6300ESB I/O Controller Hub...
Page 561: Offset 3Dh: Intr_Pn-Interrupt Pin Register (Audio-D31:F5)
0, bits ’0’ and ‘1’, upon an I/O access to (SCID) the secondary codec. Bit ’1’ is the first bit sent and bit ’0’ is the second bit sent on AC_SDATA_OUT during slot 0. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 562: Offset 41H: Cfg-Configuration Register (Audio-D31:F5)
15:8 Next Capability (NEXT) Indicates that the next item in the list is at offset 00h. Indicates that this pointer is a message signaled interrupt Cap ID (CAP) capability. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 563: Offset 52H: Pc-Power Management Capabilities Register (Audio-D31:F5)
This bit is set when the AC’97 controller would normally PME Status (PMES) assert the PME# signal independent of the state of the R/WC PME_En bit. This bit resides in the resume well. 14:9 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 564 The AC’97 I/O space includes Native Audio Bus Master Registers and Native Mixer ® Registers. For the Intel 6300ESB ICH, the offsets are important as they will determine bits[1:0] of the TAG field (codec ID). Audio Mixer I/O space may be accessed as a 16-bit field only since the data packet length on AC-link is a word.
Page 565: Intel ® 6300Esb I/O Controller Hub Audio Mixer Register Configuration
® 13—Intel 6300ESB ICH ® Table 483. Intel 6300ESB I/O Controller Hub Audio Mixer Register Configuration (Sheet 1 of 2) Primary Offset Secondary Offset Tertiary Offset NAMBAR Exposed Registers (Codec ID =00) (Codec ID =01) (Codec ID =10) (D31:F5) 100h...
Page 566: Native Audio Bus Master Control Registers
® Intel 6300ESB ICH—13 ® Table 483. Intel 6300ESB I/O Controller Hub Audio Mixer Register Configuration (Sheet 2 of 2) Primary Offset Secondary Offset Tertiary Offset NAMBAR Exposed Registers (Codec ID =00) (Codec ID =01) (Codec ID =10) (D31:F5) 15Ah...
Page 567 PCM In 2 Control Register S/PDIF Buffer Descriptor List Base Address 60-63 SP_BAR 00000000h Register SP_CIV S/PDIF Current Index Value SP_LVI S/PDIF Last Valid Index 66-67h SP_SR S/PDIF Status Register 0001h ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 568: X_Bdbar-Buffer Descriptor Base Address Register
32-bit read from address offset 04h. Software may also read this register individually by doing a single 8-bit read to offset 04h. Reads across dWord boundaries are not supported. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 569: X_Lvi-Last Valid Index Register
32-bit read from address offset 04h. Software may also read this register individually by doing a single 8-bit read to offset 05h. Reads across dWord boundaries are not supported. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 570 ® The Intel 6300ESB ICH will set the FIFOE bit if the underrun or overrun occurs when there are more valid buffers to process. 0 = Cleared by writing a “1” to this bit position.
Page 571: X_Picb-Position In Current Buffer Register
These bits represent which buffer descriptor in the list has Prefetched Index been prefetched. The bits in this register are also modulo 32 Value[4:0] and roll over after they reach 31. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 572: X_Cr-Control Register
(i.e., master mode operation (RPBM) may be stopped and then resumed). 1 = Run. Bus master operation starts. 13.2.8 GLOB_CNT—Global Control Register Note: Reads across dWord boundaries are not supported. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 573: Glob_Cnt—Global Control Register
AC_SDIN[0] causes a resume event on the AC-link. 0 = Normal operation. ACLINK Shut Off (LSO) 1 = Controller disables all outputs which will be pulled low by internal pull down resistors. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 574: Glob_Sta-Global Status Register
1 = The change on value of a GPI causes an interrupt and sets bit ’0’ of the Global Status Register. 13.2.9 GLOB_STA—Global Status Register Note: Reads across dWord boundaries are not supported. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 575: Glob_Sta—Global Status Register
Indicates that the bit clock is not running. This bit is set when ® the Intel 6300ESB ICH detects that there has been no Bit Clock Stopped (BCS) transition on BIT_CLK for four consecutive PCI clocks. It is cleared when a transition is found on BIT_CLK.
Page 576 This bit indicates that one of the Mic in channel interrupts Mic In Interrupt (MINT) status bits has been set. When the specific status bit is cleared, this bit will be cleared. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 577 R/WC in slot 12. The bit is cleared by software writing a ‘1’ to this Interrupt (GSCI) bit location. This bit is not affected by D3 to D0 Reset. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 578: 13.2.10 Cas-Codec Access Semaphore Register
PCM In 1 and Mic In 1 engines use the OR’d AC_SDIN lines. PCM In 1, Microphone In 1 Data In Line (DI1L) 00 AC_SDIN0 01 AC_SDIN1 10 AC_SDIN2 11 Reserved ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 579 Software may use this to determine how the codecs are mapped. The values are: Last Codec Read Data AC_SDIN0 Input (LDI) AC_SDIN1 AC_SDIN2 Reserved ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 580 ® Intel 6300ESB ICH—13 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 581: Ac'97 Modem Controller Registers (D31:F6)
NOTES: ® 1. Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to-date value of the Revision ID Register. Note: Internal reset as a result of D3 to D0 transition will reset all the core well registers except the following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0 transition.
Page 582: Offset 00 - 01H: Vid-Vendor Identification Register (Modem-D31:F6)
Power Well: Bits Name Description Access 15:0 Vendor ID Value 16-bit field indicating the company vendor as Intel 14.1.2 Offset 02 - 03h: DID—Device Identification Register (Modem—D31:F6) Table 498. Offset 02 - 03h: DID—Device Identification Register (Modem—D31:F6) Device: Function: 02 - 03h...
Page 583: Offset 04 - 05H: Pcicmd-Pci Command Register (Modem-D31:F6)
0 = Disable access (default = 0). I/O Space (IOS) 1 = Enable access to I/O space. The Native PCI Mode Base Address register should be programmed prior to setting this bit. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 584: Offset 06 - 07H: Pcista-Device Status Register (Modem-D31:F6)
6300ESB ICH's DEVSEL# ® DEVT (DEVSEL# Timing timing parameter. These read-only bits indicate the Intel 10:9 Status) 6300ESB ICH's DEVSEL# timing when performing a positive decode. DPD (Data Parity Not implemented. Hardwired to ‘0’. Detected) ® FBC (Fast Back to back Hardwired to ‘1’.
Page 585: Offset 08H: Rid-Revision Identification Register (Modem-D31:F6)
Power Well: Bits Name Description Access ® Refer to the Intel 6300ESB I/O Controller Hub Specification Revision ID Value Update for the most up-to-date value of the Revision ID Register. 14.1.6 Offset 09h: PI—Programming Interface Register (Modem—D31:F6) Table 502. Offset 09h: PI—Programming Interface Register (Modem—D31:F6)
Page 586: Offset 0Bh: Bcc-Base Class Code Register (Modem-D31:F6)
In the case of split codec implementation, accesses to the different codecs are differentiated by the controller by using address offsets 00h - 7Fh for the primary codec and address offsets 80h - FEh for the secondary codec. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 587: Offset 14 - 17H: Mbar-Modem Base Address Register (Modem-D31:F6)
128 bytes for this base address. Reserved Reserved. Read as ‘0’. Resource Type Indicator This bit is set to ‘1’, indicating a request for I/O space. (RTE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 588: Offset 2C - 2Dh: Svid-Subsystem Vendor Id (Modem-D31:F6)
The write to this register should be combined with the write to the SVID to create one 32-bit write. This register is not affected by D3HOT to D0 reset. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 589: Offset 2E - 2Fh: Sid-Subsystem Id (Modem-D31:F6)
Lockable: Power Well: Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is used to Interrupt Line communicate to software the interrupt line that the interrupt pin is connected to. ® Intel 6300ESB I/O Controller Hub...
Page 590: Offset 3Dh: Int_Pin-Interrupt Pin (Modem-D31:F6)
Description Access 15:8 Next Capability (NEXT) Indicates that this is the last item in the list. Indicates that this pointer is a message signaled interrupt Cap ID (CAP) capability. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 591: Offset 52H: Pc-Power Management Capabilities Register (Modem-D31:F6)
This bit is set when the AC’97 controller would normally PME Status (PMES) assert the PME# signal independent of the state of the RW/C PME_En bit. This bit resides in the resume well. 14:9 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 592 When software attempts to write a value of 10b or 01b to this field, the write operation must complete normally. However, the data is discarded and no state change occurs. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 593: Intel ® 6300Esb I/O Controller Hub Modem Mixer Register Configuration
2. Software should not try to access reserved registers. ® 3. The Intel 6300ESB ICH supports a modem codec connected to AC_SDIN[2:0] as long as the ® Codec ID is 00 or 01. However, the Intel 6300ESB ICH does not support more than one ®...
Page 594: Modem Registers
Offset 44h – Codec Access Semaphore Register (CAS) Resume Well registers and bits will not be reset by the D3 to D0 transition: • Offset 40h-43h – bits[17:16] Global Status (GLOB_STA) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 595: X_Bdbar-Buffer Descriptor List Base Address Register
These bits represent which buffer descriptor within the list of Current Index Value 16 descriptors is being processed currently. As each [4:0] descriptor is processed, this value is incremented. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 596: X_Lvi-Last Valid Index Register
® The Intel 6300ESB ICH will set the FIFOE bit if the under- run or overrun occurs when there are more valid buffers to process. 0 = Cleared by writing a ‘1’ to this bit position.
Page 597: X_Picb-Position In Current Buffer Register
Size: Core Lockable: Power Well: Bits Name Description Access Position In Current These bits represent the number of samples left to be 15:0 Buffer[15:0] processed in the current buffer. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 598 ® Intel 6300ESB ICH—14 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 599: X_Piv-Prefetch Index Value Register
FIFO Error Interrupt 0 = Disable. Bit 4 in the Status Register will be set, but the Enable (FEIE) interrupt will not occur. 1 = Enable. Interrupt will occur. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 600: Glob_Cnt-Global Control Register
AC_SDIN[0] causes a resume event on the AC-link. 0 = Normal operation. ACLINK Shut Off (LSO) 1 = Controller disables all outputs which will be pulled low by internal pull down resistors. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 601: Glob_Sta-Global Status Register
(with all ‘F’s on the data) and also set the Read Completion Status bit in the Global Status Register. Reads across dWord boundaries are not supported. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 602: Glob_Sta—Global Status Register
Indicates that the bit clock is not running. This bit is set when ® the Intel 6300ESB ICH detects that there has been no Bit Clock Stopped (BCS) transition on BIT_CLK for four consecutive PCI clocks. It is cleared when a transition is found on BIT_CLK.
Page 603 AC_SDIN0 Codec Ready Once the codec is “ready”, it must never go “not ready” (S0CR) spontaneously. 0 = Not Ready. 1 = Ready. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 604: 14.2.10 Cas-Codec Access Semaphore Register
1 = The act of reading this register sets this bit to 1. The Semaphore (CAS) (special) driver that read this bit may then perform an I/O access. Once the access is completed, hardware automatically clears this bit. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 605: Memory-Mapped Registers
Reserved 100-107h Timer 0 Config and Capabilities Read/Write 108-10Fh Timer 0 Comparator Value Read/Write 110-11Fh Reserved 120-127h Timer 1 Config and Capabilities Read/Write 128-12Fh Timer 1 Comparator Value Read/Write ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 606: Offset 000-007H: General Capabilities And Id Register
(10^-15 seconds). This will return 0429B17F when read. This indicates a period of 69841279 fs (69.841279 ns). 31:1 This is a 16-bit value assigned to Intel. These bits will return VENDOR_ID_CAP 8086h when read. Legacy Rout Capable: This bit will return a ’1’ when read, LEG_RT_CAP indicating that the Legacy Interrupt Rout option is supported.
Page 607: Offset 010-017H: General Config Register
Software must write to the Txx_INT_STS bits to clear the interrupts. NOTE: This bit will default to ‘0’. BIOS may set it to ’1’ or ‘0’. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 608: Offset 020-027H: General Interrupt Status Register
Software should always write ’0’ to this bit. NOTE: Defaults to ‘0’. In edge-triggered mode, this bit will always read as ’0’ and writes will have no effect. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 609: Offset 0F0 - 0F7H: Main Counter Value
(unless the timer has rolled over to ‘0’). 15.1.6 Timer n Config and Capabilities Note: The letter n may be 0, 1, or 2, referring to Timer 0, 1 or 2. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 610: Timer N Config And Capabilities
‘1’. All other bits will be ‘0’. TIMERn_INT_ROUT_CAP ® Intel 6300ESB ICH and Timer 0, 1 Specific: Bits 20, 21, 22, 63:3 and 23 in this field (corresponding to bits 52, 53, 54, and 55 TIMERn_INT_ROUT[31: in this register) will have a value of ‘1’.
Page 611 (20, 21, 22, or 23) for this field. ® The Intel 6300ESB ICH logic does not check the validity of the value written. 3. Timer 2 Specific: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this ®...
Page 612 That delay is not known at this time. Supports edge and level triggered modes for all three timers. Reserved Reserved. These bits will return ’0’ when read. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 613: Timer N Comparator Value
4. Default value for each timer is all ones for the bits that are implemented. For example, a 32-bit timer will have a default value of 00000000FFFFFFFFh. A 64-bit timer will have a default value of FFFFFFFFFFFFFFFFh. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 614 ® Intel 6300ESB ICH—15 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 615: Product Features
Note: The WDT device (Dev 29:F4) cannot be hidden by using bit 12 of the D31:F0 FUNC_DIS Register. The WDT will always be present as a PCI device in PCI Config Space. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 616: Wdt Block Diagram
35-bit down-counter until the next time the WDT reenters the stage. For example, when Preload Value 2 is changed, it is not loaded into the 35-bit down- counter until the next time the WDT enters the second stage. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 617: Wdt Interface
10-13h Base Address Register (BAR) 00000000h Read/Write ® NOTE: Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to- date value of the Revision ID register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 618: Memory Mapped Registers
Manufacturer’s ID 00000F66h Read Only FC-FFh Reserved ® NOTE: Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to- date value of the Revision ID register. 16.4.2 Memory Mapped Registers Table 537. Memory Mapped Registers Offset Register...
Page 619: Offset 02H: Did-Device Identification Register
If this bit is set, accesses to the WDT’s Memory Enable Mapped registers are enabled. The Base Address register for WDT should be programmed before this bit is set. IOSE - I/O Space Enable Reserved as ‘0’. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 620: Offset 06H - 07H: Ds-Device Status Register
This bit is set when the function is targeted with a transaction STA - Signaled Target- ® that the Intel 6300ESB ICH terminates with a target abort. R/WC Abort Status Software resets STA to ’0’ by writing a ’1’ to this bit location.
Page 621: Offset 08H: Rid—Revision Identification Register
6300ESB ICH 16.4.7 Offset 08h: RID—Revision Identification Register ® Note: Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up- to-date value of the Revision ID. Table 542. Offset 08h: RID—Revision Identification Register Device: Function: Read-Only...
Page 622: 16.4.10 Offset 0Bh: Bcc-Base Code Class Register
16.4.11 Offset 0Eh: HEDT—Header Type Register Note: The Base Address Register points to several memory mapped registers for the Watchdog Timer. It decodes the smallest possible region of 16 Bytes. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 623: 16.4.12 Offset 10H: Bar-Base Address Register
Note: Software (BIOS) will write the value to this register. After that, the value may be read, but writes to the register will have no effect. The write to this register should be combined with the write to the SID to create one 32-bit write. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 624: Offset 2Eh - 2Fh: Sid—Subsystem Id
Table 549. Offset 2Eh - 2Fh: SID—Subsystem ID Device: Function: 2Eh-2Fh Read, Write Once Offset: Attribute: 16-bit Default Value: Size: Core Lockable: Power Well: Bits Name Description Access 15:0 Subsystem ID ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 625: 16.4.15 Offset 60 - 61H: Wdt Configuration Register
00 = IRQ (APIC 1, INT 10) (Default) WDT_INT_TYPE 01 = Reserved 10 = SMI 11 = Disabled IRQ is Active low, level triggered 16.4.16 Offset 68h: WDT Lock Register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 626: Offset 68H: Wdt Lock Register
0 = Unlocked (Default) WDT_LOCK R/WO 1 = Locked This is a Write-Once bit. It cannot be changed until either power is cycled or a hard reset occurs. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 627: 16.4.17 Offset F8 - Fbh: Manufacturer's Id
(i.e., zero is counted as part of the decrement). Please refer to Section 16.5.2, “Register Unlocking Sequence” for details on how to change the value of this register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 628: Offset Base + 04H: Preload Value 2 Register
This is a sticky bit and is only cleared by writing a 1. Interrupt Active: 0 = No Interrupt 1 = Interrupt Active NOTE: This bit is not set in free-running mode. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 629: Offset Base + 0Ch: Reload Register
The WDT_TOUT# pin is then toggled LOW by the WDT ® from the Intel 6300ESB ICH. The board designer should attach the WDT_TOUT# to the appropriate external signal. When WDT_TOUT_CNF is a ’1’ the WDT toggles WDT_TOUT# again when the next timeout occurs. Otherwise, WDT_TOUT# is driven low until the system is reset or power is cycled.
Page 630: Reload Sequence
‘1’ to bit 8 at offset BAR+ 0Ch within the watchdog timer memory mapped space. This sequence of events is referred to as the “Reload Sequence”. 16.5.4 Low Power State The Watchdog Timer does not operate when PCICLK is stopped. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 631: Apic1 Configuration Map (D29:F5)
(D29:F5) APIC1’s direct registers are assigned with base address FEC1xxxxH. To support legacy device/driver on external PCI bus used with the Intel ICHx, APIC1 has an alternate base address FEC0xxxxH. This means external PCI devices may write to IRQ pin assertion register (either FEC0_0020H or FEC1_0020H) to generate interrupt from APIC1.
Page 632: Offset 00 - 03H: Vid_Did-Vendor/Id Register (Apic1-D29:F5)
Device ID Value This is a 16-bit value assigned to the APIC1. DID = 25ACh 15:0 Vendor ID Value This is a 16-bit value assigned to Intel. Intel VID = 8086h 17.1.2 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—D29:F5) Table 559.
Page 633: Offset 06 - 07H: Apic1Sta-Apic1 Device Status (Apic1-D29:F5)
Access 0 = No action is taken when detecting a parity error. ® 1 = The Intel 6300ESB ICH will take normal action when a parity error is detected. PERE: Parity Error Response Enable NOTE: D30FO offset F4h, bit #2 must be set to a ‘1’ AND D28FO offset F4h, bit #2 must be set to a ‘1’...
Page 634: Offset 08H: Rid-Revision Id Register (Apic1-D29:F5)
Size: Bits Name Description Access ® Refer to the Intel 6300ESB I/O Controller Hub Specification Revision ID Value Update for the most up-to-date value of the Revision ID Register. 17.1.5 Offset 09 - 0Bh: CC—Class Code Register (APIC1— D29:F5) Table 562. Offset 09 - 0Bh: CC—Class Code Register (APIC1—D29:F5)
Page 635: Offset 0C - 0Fh: Headtyp-Header Type Register (Apic1-D29:F5)
Power Well: Bits Name Description Access 31:1 SSID: Subsystem ID Write once register for subsystem ID. SSVID: Subsystem 15:0 Write once register for holding the subsystem vendor ID. Vendor ID ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 636: Offset 34H: Cap_Ptr-Apic1 Capabilities Pointer (Apic1-D29:F5)
Bits Name Description Access ® This data is not used by the Intel 6300ESB ICH. It is used as 17:0 ILINE: Interrupt Line a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to.
Page 637: Offset 40 - 41H: Abar-Apic1 Alternate Base Address Register (Apic1-D29:F5)
6300ESB ICH that matches FECX_YZ00 or FECX_YZ10, (XBAD) ® the Intel 6300ESB ICH will respond to the cycle and access the internal I/O APIC1. These bits determine the low order bits of the I/O APIC address map. When a memory address is recognized by the Base Address [15:12] ®...
Page 638: Offset 44 - 47H: Mbar—Apic1 Memory Base Register (Apic1—D29:F5)
Indicates that the BAR is not pre-fetchable. '00' indicates that the address may be located anywhere in LOC: Location the 32-bit address space. SI: Space Indicator Indicates that the BAR is in memory space. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 639: Offset 50 - 51H: Xid-Pci-X Identifiers Register (Apic1-D29:F5)
Reflects the device number that has been hard-coded for the Device Number device. This number will be 1Dh (29) for APIC1. Function Number Reflects the function number for the device. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 640: Apic1 Direct Registers
17.2 Advanced Interrupt Controller (APIC) There are two APICs in the Intel® 6300ESB ICH: APIC0 and APIC1 (in device 29, function 5). APIC0’s direct registers are assigned with base address FEC0xxxxH; however, no external PCI device may write to these registers. APIC1’s direct registers are assigned with base address FEC1xxxxH.
Page 641: Ind-Index Register
To provide for future expansion, peripherals should always write a value of 0 for Bits 31:5. ® Note: Writes to this register are only allowed by the processor and by masters on the Intel ® 6300ESB ICH’s PCI bus. Writes by devices on PCI buses above the Intel 6300ESB ICH (e.g., a PCI segment on a P64H) are not supported.
Page 642: Eoir-Eoi Register
’0’ to Bits 31:8. Vector to be compared with vector field in the I/O redirection End of Interrupt (EOI) table when an EOI is issued. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 643: Offset 00H: Id-Identification Register
14:8 Reserved Reserved. This is a version number that identifies the implementation ® Version version. The version number assigned to the Intel 6300ESB ICH for the I/O (x) APIC is 20h. ® Intel 6300ESB I/O Controller Hub November 2007...
Page 644: Offset 03H: Boot_Config-Boot Configuration Register
Reserved. Software should program these bits to 0. This bit is maintained for any potential software compatibility, Disable Flushing ® but the Intel 6300ESB ICH performs no flushing action, (DFLSH) regardless of the setting of this bit. ® Intel 6300ESB I/O Controller Hub...
Page 645 Destination Mode 1 = Logical. Destinations are identified by matching bit [63:56] with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 646 Requires the interrupt to be programmed as edge triggered. The Remote IRR bit is never set if programmed for ExtINT level-triggered operation; as a result a continuous stream of interrupts will be generated as long as the INTR input is asserted. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 647: Pci-X Overview (D28:F0)
Kbytes and is aligned on a 4 Kbyte boundary. The maximum I/O range is 64 Kbytes. ® This range may be lowered to 1K granularity by setting the EN1K bit in the Intel 6300ESB ICH Configuration register at offset 40h.
Page 648: Memory Window Addressing
® 04-05h). The Intel 6300ESB ICH does not prefetch data from PCI devices. The Intel 6300ESB ICH supports 64 bits of addressing (DAC cycles) on both interfaces. 18.2.1 Memory Base and Limit Address Registers The memory base address and memory limit address registers define an address range ®...
Page 649: Vga Addressing
6300ESB ICH bridge, the VGA ® enable bit in the bridge control register is set (offset 3 at 3E-3Fh). When set, the Intel 6300ESB ICH forwards all transactions addressing the VGA frame buffer memory and VGA I/O registers from the Hub Interface to PCI-X, regardless of the values of the ®...
Page 650: Configuration Addressing
Type 1 to Type 0 Translation ® The Intel 6300ESB ICH performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the Hub Interface and is intended for a device attached ® directly to the secondary bus. The Intel 6300ESB ICH must convert the configuration command to a Type 0 format so that the secondary bus device may respond to it.
Page 651: Type '1' To Type '0' Translation
Hub Interface and target PCI/PCI-X. ® The Intel 6300ESB ICH translates a Type 1 configuration transaction into a Type 0 transaction under the following conditions: • The bus command is a Configuration read or write transaction.
Page 652: Comparison Of Rules Vs. A Pci - Pci Bridge
2. In a bridge, these are allowed to be yes/no. 3. In a bridge, these are allowed to be yes/no. These particular entries are “No” because the ® Intel 6300ESB ICH does not accept inbound write requests that are not posted (I/O writes, configuration writes). 18.5.2 Other Notes Ordering relationships are established for the following classes of transactions crossing ®...
Page 653: Configuration Space Register Summary
PCI-X Upstream Split Transaction PX_USTC 0000FFFFh Control ® NOTE: Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to- date value of the Revision ID register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 654: 18.6.1.2 Offset 00: Id-Identifiers
Reserved 7B7BBFFFh ® NOTE: Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to- date value of the Revision ID register. 18.6.1.2 Offset 00: ID—Identifiers Note: Contains the vendor and device identifiers for software. Table 585. Offset 00: ID—Identifiers...
Page 655: 18.6.1.3 Offset 04: Cmd-Command
® Controls the Intel 6300ESB ICH's response when a parity error is detected on the Hub Interface. ® 0 = The Intel 6300ESB ICH ignores these errors on the Hub Parity Error Interface. Response ® 1 = The Intel 6300ESB ICH reports these errors on the Hub Enable Interface and sets the DPD bit in the status register.
Page 656: 18.6.1.4 Offset 06: Psts-Primary Status
Hub Interface when forwarding memory Bus Master transactions from PCI-X. Enable ® When '0': the Intel 6300ESB ICH does not respond to any (BME) memory transactions on the PCI-X interface that target Hub Interface. Memory ® Controls the ability of the Intel...
Page 657: Devsel# Timing
Name Description Access Value ® When set to 1, this bit indicates that the Intel 6300ESB ICH detected an address parity, data parity, error on the Hub Interface. This bit gets set even when the Parity Error Detected Response bit (bit 6 of the command register) is not set. Note...
Page 658: 18.6.1.5 Offset 08: Rid-Revision Id
Size: Reset Bits Name Description Access Value ® Refer to the Intel 6300ESB I/O Controller Hub Specification Revision ID 07:0 Update for the most up-to-date value of the Revision ID (RID) register. ® Intel 6300ESB I/O Controller Hub November 2007...
Page 659: 18.6.1.6 Offset 09: Cc-Class Code
Description Access Value ® The value in this register is used by the Intel 6300ESB ICH to determine the size of packets on the Hub Interface. This read/write register specifies the system cache line size in units of dWords. When the value is ‘08h’, represents a 32- byte line (8 dWords).
Page 660: 18.6.1.8 Offset 0D: Plt-Primary Latency Timer
Defines the layout of addresses 10h through 3Fh in Header configuration space. Reads as ‘01h’ to indicate that the 06:0 Type register layout conforms to the standard PCI-to-PCI bridge (HTYPE) layout. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 661: Offset 18: Bnum—Bus Numbers
PXFRAME#. When the grant is removed, the expiration of this counter results in the ® deassertion of PXFRAME#. When the grant has not been removed, the Intel 6300ESB ICH may continue ownership of the bus. The secondary latency timer's default value should be 64 in PCI-X mode (Section 8.6.1 of the PCI-X 1.0 Specification).
Page 662: Offset 1C: Iobl—I/O Base And Limit
These bits correspond to address lines 15:12 for 4 [15:12] Kbyte alignment. Bits 11:0 are assumed to be FFFh. (IOLA) ® I/O Limit When the EN1K bit is set in the Intel 6300ESB ICH Address Configuration register (CNF), these bits become read/write 11:1 Bits...
Page 663: Offset 1E: Ssts—Secondary Status
10:9 Timing decode time to all cycles targeting the Hub Interface. (DVT) ® The Intel 6300ESB ICH sets this bit when all of the following are true: Data Parity ® • The Intel 6300ESB ICH is the initiator on PCI-X.
Page 664: Offset 20: Mbl—Memory Base And Limit
1 Mbyte aligned value 000h Base (MB) (inclusive) of the range. The incoming address must be greater than or equal to this value. 03:0 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 665: Offset 24: Pmbl—Prefetchable Memory Base And Limit
All bits are read/writable. e Memory 31:0 This register should always be programmed to 00000000h Base Upper 00000000h ® since the Intel 6300ESB ICH only supports 32-bit Portion downstream addressing and 64-bit upstream addressing (PMBU) ® Intel 6300ESB I/O Controller Hub November 2007...
Page 666: Offset 2C: Pmlu32—Prefetchable Memory Limit Upper 32 Bits
Reset Bits Name Description Access Value ® All bits are read/writable - the Intel 6300ESB ICH supports full 64-bit addressing. NOTE: The upper 32 bits should not be used to determine the ® prefetch region. The Intel 6300ESB ICH supports...
Page 667: Offset 34: Capp—Capabilities List Pointer
Pin (PIN) ® 07:0 Interrupt The Intel 6300ESB ICH Bridge does not generate interrupts, Line (LINE) so this is reserved as 00h. 18.6.1.21Offset 3E: BCTRL—Bridge Control Note: This register provides extensions to the Command register that are specific to a bridge.
Page 668: Offset 3E: Bctrl—Bridge Control
® Sets the maximum number of PCI clock cycles that the Intel 6300ESB ICH waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the delayed transaction completion is at the head of the queue. If the...
Page 669 Modifies the Intel 6300ESB ICH's response to VGA ® compatible address. When set to a 1, the Intel 6300ESB ICH forwards the following transactions from the Hub Interface to PCI-X regardless of the value of the I/O base and limit registers.
Page 670 768 bytes in each 1 Kbyte block (offsets 100h to 3FFh). This bit has no effect on transfers originating ® on the secondary bus as the Intel 6300ESB ICH does not forward I/O transactions across the bridge.
Page 671: Offset 40: Cnf—Intel 6300Esb I/O Controller Hub Configuration
® 18—Intel 6300ESB ICH ® 18.6.1.22Offset 40: CNF—Intel 6300ESB I/O Controller Hub Configuration Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration (Sheet 1 of 3) Device Function Read/Write Offset Attribute: 16-bit Size: Reset Bits Name Description Access Value Reserved Reserved.
Page 672 ® Intel 6300ESB ICH—18 Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration (Sheet 2 of 3) Device Function Read/Write Offset Attribute: 16-bit Size: Reset Bits Name Description Access Value Determines the frequency the PCI-X bus operates. The power...
Page 673: Offset 42: Mtt—Multi-Transaction Timer
® 18—Intel 6300ESB ICH Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration (Sheet 3 of 3) Device Function Read/Write Offset Attribute: 16-bit Size: Reset Bits Name Description Access Value ® Controls how the Intel 6300ESB ICH prefetches data on behalf of PCI masters: 00: Allow prefetching on MRM, MRL, and MR.
Page 674: Offset 44: Strp—Pci Strap Status
Note: Indicates where the next item in the capabilities list resides. This is the end of the list and 00h is returned. Table 609. Offset 51: PX_NXTP—Next Item Pointer Device Function Read-Only Offset Attribute: 8-bit Size: Reset Bits Name Description Access Value 07:0 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 675: Offset 52: Px_Ssts—Pci-X Secondary Status
Delayed. Transaction Control register. (SRD) ® NOTE: The Intel 6300ESB ICH does not set this bit. This bit is set when a bridge terminates a Split Completion on Split the secondary bus with retry or Disconnect at next ADB Completion because its buffers are full.
Page 676: Offset 54: Px_Bsts - Pci-X Bridge Status
The Intel 6300ESB ICH does not support this bit. Delayed (SRD) Split ® The Intel 6300ESB ICH does not set this bit because it does Completion not request more data on the Hub Interface than it may Overrun receive. (SCO) Unexpected...
Page 677 Available for diagnostic software. (BNUM) Device 07:0 Default value is device 28. Readable from separate PCI-X Number diagnostic software. (DNUM) Function 02:0 Number Read-only bits for PCI-X diagnostic software. (FNUM) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 678: Offset 58: Px_Ustc - Pci-X Upstream Split Transaction Control
Split Transactions from the secondary bus to the Hub Interface. ® Note: The Intel 6300ESB ICH maintains these registers internally; programming is not required by end users. Table 612. Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control Device...
Page 679: Offset 5C: Px_Dstc - Pci-X Downstream Split Transaction Control
Reset Bits Name Description Access Value R/W field available for use by diagnostic software. Split ® NOTE: Not used by the Intel 6300ESB ICH for modifying its 31:1 Transaction ® 0000h “commitment” level. The Intel 6300ESB ICH internal Limit (STL) launch algorithms keep buffers from being overallocated.
Page 680: Offset E0: Acnf – Additional Intel 6300Esb Ich Configuration
® Intel 6300ESB ICH—18 ® 18.6.1.31Offset E0: ACNF – Additional Intel 6300ESB ICH Configuration Table 614. Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration Device Function Read-Only Offset Attribute: 32-bit Size: Reset Bits Name Description Access Value 31:1 Reserved Reserved.
Page 681: Offset E4: Pcr - Pci Compensation Register
1 = PCI-X secondary bus reset (PCIXSBRST#) enabled and SBR is set. NOTE: Processor always writes a ’1’ into this bit and enables the secondary bus reset for the PCI-X bus. 08:0 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 682: Offset F0: Hccr - Hub Interface Command/Control Register
A fetch of one cache line (based upon the cache line size register) is performed and when it drains, the delayed transaction is complete. A new delayed transaction is established when the master wished the burst to continue. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 683: Offset F8H: Pc33 - Prefetch Control – 33 Mhz
07:0 Threshold Initial threshold size in 64-byte cache lines. (TI) Initial 03:0 Initial request size in 64-byte cache lines. Allowable Request programmable values are 00h or 01h only. (RI) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 684: Pci Mode In The Pci-X Interface
1111 Invalidate ® † The Intel 6300ESB ICH never initiates a PCI transaction with a reserved command code and ignores reserved command codes as a target. ® As a PCI master, the Intel 6300ESB ICH has access to the 32-bit address space. As a ®...
Page 685: Data Bus
PXDEVSEL# active, then the Intel 6300ESB ICH downshifts the all byte enables PXC/ BE#[3:0]. ® The Intel 6300ESB ICH does not assert REQ64# when initiating a transfer under the following conditions: • ® The Intel 6300ESB ICH is initiating an I/O transaction.
Page 686: Read Transactions
Delayed write forwarding is not used. It is only for I/O write transactions. Since the ® Intel 6300ESB ICH does not support I/O write transactions across a bridge, these cycles all result in a master abort. Note: Configuration cycles are not allowed to cross a bridge per the PCI bridge specification.
Page 687: Error Handling
6300ESB ICH receives a target abort, and the cycle requires completion on the Hub Interface, the ® Intel 6300ESB ICH returns the target abort code to the Hub Interface as the completion status. ® 18.7.7.4 Target Termination Initiated by the Intel 6300ESB ICH ®...
Page 688 • Primary status (offset 06-07h) and secondary status registers (offset 1E-1Fh) ® The Intel 6300ESB ICH does not have the PERR# or SERR# pins on the Hub ® Interface. The Intel 6300ESB ICH is capable of generating NMI, and SMI...
Page 689 18.7.9.1.2 Read Transactions from Hub Interface Targeting PCI on the PCI-X ® When the Intel 6300ESB ICH detects a read data parity error on the PCI bus from a Hub Interface initiated read, it: • Sets the detected parity error bit in the secondary status register (bit 15 of offset 1E-1Fh).
Page 690: System Errors
— The primary interface parity error response bit is set in the command register. ® — The Intel 6300ESB ICH did not detect the parity error on the Hub Interface (i.e., the parity error was not forwarded from the Hub Interface). 18.7.9.2 System Errors 18.7.9.2.1 PCI SERR# Pin Assertion...
Page 691: Pci-X Interface
This section is not intended to describe the PCI-X protocol. It is intended to clarify the ® Intel 6300ESB ICH behavior in areas of the specification which are open to interpretation. Please see the PCI-X Addendum to the PCI specification, revision 1.0 for all details related to PCI-X operation.
Page 692: Special Notes For Burst Transactions
The PCI-X specification allows burst transactions to cross page (in the Intel 6300ESB ® ICH’s case, this is 4K) and 4 Gbyte address boundaries. As a PCI-X master, the Intel ® 6300ESB ICH ends the transaction at a 4K boundary. As a PCI-X target, the Intel 6300ESB ICH allows a burst past a 4K page boundary.
Page 693: Intel ® 6300Esb Ich Implementation Completer Attribute Fields
18.8.6.3 Split Completion Messages ® The Intel 6300ESB ICH may only generate error messages for cycles that cross the bridge that master or target abort. No DWORD cycles cross the bridge that require ® completion (i.e., I/O cycles). Therefore, the Intel 6300ESB ICH generates a “PCI-X...
Page 694: Transaction Termination As A Pci-X Target
® The Intel 6300ESB ICH retries a cycle when the Split Request queue is full (i.e., we already have four current and four pending Split Transactions). It has room to accept a split completion as it has a dedicated buffer for split completions. It also retries a cycle ®...
Page 695: Immediate Terminations Of Completion Required Cycles To Pci/Pci-X
18.8.11.2Special Parity Error Rule for Split Response ® When the Intel 6300ESB ICH calculates a data parity error when a target signals Split Response for a read transaction, it records the error as described in section 5.4.1 of the ®...
Page 696: Immediate Terminations Of Posted Write Cycles To Pci/Pci-X
“write data parity error”, “device specific”, and reserved/illegal codes. The ® Intel 6300ESB ICH must not lock its bus on these errors, even though they are not explicitly master or target aborts on the PCI-X interface. Table 627. Split Terminations of Completion Required Cycles to PCI-X (Sheet 1 of...
Page 697: Hub Interface Response To Pci-X Split Completion Terminations Of Completion Required Cycles
PCI-X Split Completions ® The following table indicates what the Intel 6300ESB ICH does when it is returning a split completion to PCI-X from a normal Hub Interface completion, and receives an immediate response indicating some kind of error. Table 628. Hub Interface Response to PCI-X Split Completion Terminations of...
Page 698: Behavior Of Pci/Pci-X Initiated Cycles To Hub Interface
Interface. When several bytes of data returned successfully from the Hub Interface and have ® not yet been sent back on PCI-X, when the abort is detected on the Hub Interface the Intel 6300ESB ICH stops the current sequence for that data (if it was running) and generates the Split Completion Error Message.
Page 699: Prefetch Algorithm
When B < Ts, wait for timer to expire before launch of size Rs. Restart timer. Go to Step 4. When B > Ts before timer expires, reset timer. Go to Step 5. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 700: Algorithm (Multiple Pci-X Devices Requesting)
When multiple agents are requesting in PCI-X mode, the ® Intel 6300ESB ICH needs to switch between these agents for completions. It does this by utilizing its MLT parameter. When the MLT expires, it stops this stream and switches to another stream.
Page 701: Data Return Behavior Of Hub Interface Initiated Reads
® For all Hub Interface initiated memory read cycles targeting PCI/PCI-X, the Intel 6300ESB ICH ensures a return length of a naturally aligned 128-bytes. When a request ® is less than 128 bytes and within a single 128-byte line, the Intel 6300ESB ICH ®...
Page 702: Active Master Clock Counts
First word latency is measured as the number of clocks from the initial assertion of PXFRAME# (this is clock 0) to the first clock on which valid data is returned in response to the request. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 703: Serial I/O Unit
• Two serial ports Note: The serial ports of the Intel® 6300ESB ICH are not completely compatible with other 16550 standard devices. A system or software designer must follow the specifications laid out in this document above standard 16550 specifications.
Page 704: Siu Block Diagram
SERIAL OUTPUT for UART0 and UART1: Serial data output to the SIU0_TXD, communication peripheral/modem or data set. Upon reset, the TXD SIU1_TXD pins will be set to MARKING condition (logic ‘1’ state). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 705 DATA SET READY for UART0 and UART1: Active low, this pin indicates that the external agent is ready to communicate with the ® Intel 6300ESB ICH UARTs. These pins have no effect on the transmitter. NOTE: These pins could be used as Modem Status Input whose SIU0_DSR#, condition may be tested by the processor by reading bit 5 (DSR) of the Modem Status register.
Page 706: Address Map
32-bit transfer, the host must break it up into 8-bit transfers. See the Low Pin Count (LPC) Interface Specification for the sequence of cycles for the I/O Read and Write cycles. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 707: Reset Policy
— The SIU ignores LFRAME#, tristates the LAD[3:0] pins and drives the SIU’s LDRQ# signal inactive (high). ® Note: LPC bus signals from SIU are tied to primary LPC interface external to the Intel 6300ESB ICH device. Host LPC and SIU LPC names are used interchangeably throughout.
Page 708: Uart Feature List
1.8432 MHz 1.8462 MHz ® Note: Some clock chips provide a 14.318x MHz clock output. The Intel 6300ESB ICH’s UART clock must use a 14.7456 MHz frequency; most clock chips do not provide this frequency. An option will be to use the 48.0 MHz clock.
Page 709: Example Uart Data Frame
An SIU reset will force the internal register and output signals on the serial port to the values listed in Table 636. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 710: 19.5.1.3 Internal Register Descriptions
Line Status (Read only) Base + 06H Modem Status (Read only) Base + 07H Scratch Pad (R/W) Base Divisor Latch (Lower Byte, R/W) Base + 01H Divisor Latch (Upper Byte, R/W) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 711: Receive Buffer Register (Rbr)
(using the bit5: COMP) to avoid interrupt controller and DMA controller serving the receive FIFO at the same time. Note: The use of bit 4 and 5 is different from the register definition of standard 16550. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 712: Interrupt Enable Register (Ier)
641) and records these in the Interrupt Identification Register. The Interrupt Identification Register (IIR) stores information indicating that a prioritized interrupt is pending and the source of that interrupt. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 713: Interrupt Identification Register (Iir)
10 = Received Data Available 11 = Receive error (Overrun, parity, framing, break, FIFO error) Interrupt Pending: 0 = Interrupt is pending. (Active low) 1 = No interrupt is pending. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 714: Interrupt Identification Register Decode
00 = 1 byte or more in FIFO causes interrupt (same as 16550). 01 = RSVD 10 = 8 bytes or more in FIFO causes interrupt and DMA request (same as 16550). 11 = RSVD ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 715: Line Control Register (Lcr)
The programmer may also read the contents of the Line Control Register. The read capability simplifies system programming and eliminates the need for separate storage in system memory. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 716 If PEN = 0, STKYP is ignored. 0 = No effect on parity bit. 1 = Forces parity bit to be opposite of EPS bit value. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 717: Line Status Register (Lsr)
These bits are not cleared by reading the erroneous byte from the FIFO or receive buffer. They are cleared only by reading LSR. In FIFO mode, the line status interrupt ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 718 BI shows the break condition for the character at the top of the FIFO, not the most recently received character. 0 = No break signal has been received. 1 = Break signal occurred ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 719: Modem Control Register (Mcr)
This 8-bit register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the Modem Control register are described Table 647. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 720 Bit ’1’ affects the RTS# output in a manner identical to that described below for the DTR bit. 0 = RTS# pin is 1 1 = RTS# pin is 0 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 721: Modem Status Register (Msr)
1 = CTS# pin is 0 Delta Data Carrier Detect: DDCD 0 = No change in DCD# pin since last read of MSR. 1 = DCD# pin has changed state. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 722: Scratch Pad Register (Scr)
Table 650. Divisor Latch Register Low (DLL) Divisor Latch Register Low Address: Base (DLAB=1) Reset State: read/write Access: 8-bit Bit Number Bit Mnemonic Function BR[7:0] Low byte compare value to generate baud rate ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 723: Divisor Latch Register High (Dlh)
• The Transmit Data Request interrupt occurs when the transmit FIFO is half empty or more than half empty. The interrupt is cleared as soon as the Transmit Holding ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 724: Logical Device 7 (07H): Port 60/64 Emulation
Device 07 Primary Interrupt Register (70h). The interrupt generated from this unit will drive active (drives a logical 0) for one SIRQ frame. It does not require any further action (i.e., no EOI required or status bit to clear). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 725: Start Frame Timing With Source Sampled A Low Pulse On Irq1
1. H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample 2. Start Frame pulse may be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 726: Stop Frame Timing With Host Using 17 Siu_Serirq Sampling Period
Frames pulse width to determine the next SIU_SERIRQ Cycle’s mode. Each SIU port must use a dedicated interrupt. SIU interrupts cannot be shared with each other or with other devices. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 727: Siu_Serirq Sampling Periods
Continuous mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 728: Configuration
After a PCI Reset (SIU_LRESET# pin asserted) or Power On Reset the SIU is in the Run Mode with the two UARTs disabled. They may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the SIU into Configuration Mode. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 729: Configuration Mode
3. The chip returns to the RUN State. Note: Only two states are defined: Run and Configuration. In the Run State, the chip will always be ready to enter the Configuration State. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 730: Configuration Registers Summary
Base I/O Address LSB Primary Interrupt Select Reserved Reserved Vendor Specific Configuration Logical Device 7 Registers (Port Emulation) Enable Base I/O Address MSB Base I/O Address LSB Primary Interrupt Select ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 731: Global Control Registers
DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in Table 657 through Table 659. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 732: Logical Device 4 (Serial Port 0)
Registers 60h (MSB) and 61h (LSB) set the base address for the device. NOTE: Decode is on 8 Byte boundaries ® Intel 6300ESB ICH Comm Decode Ranges 3F8 - 3FF (COM 1) 2F8 - 2FF (COM 2) I/O Base Address 60-61h...
Page 733 Default = 04h (R/W - bit Bit 7:0 - RSVD 3:0) (R - bit 7:4) RSVD Default = 00h (R/W - bit 0) Bit 7:0 - RSVD (R - bit 7:1) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 734: Logical Device 5 (Serial Port 1)
Registers 60h (MSB) and 61h (LSB) set the base address for the device. NOTE: Decode is on 8 Byte boundaries. ® Intel 6300ESB ICH Comm Decode Ranges 3F8 - 3FF (COM 1) I/O Base Address 60-61h 2F8 - 2FF (COM 2)
Page 735: Logical Device 7 (Port Emulation)
(R - bit 7:4 RSVD Default = 00h (R/W - bit 0) Bit 7:0 - RSVD (R - bit 7:1) Table 659. Logical Device 7 (Port Emulation) Logical Device Address Description Register ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 736 0F = IRQ15 NOTE: An Interrupt is activated by enabling this device (offset 30h),setting this register to a non-zero value, and writing to the appropriate I/O address (60h or 64h). ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 737: Pci Configuration Map (Sata–D31:F2)
Synchronous DMA Control Register NOTES: ® 1. The Intel 6300ESB ICH SATA Controller is not arbitrated as a PCI device, therefore it does not need a master latency timer. ® 2. Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to-date value of the Revision ID register.
Page 738: Offset 00 - 01H: Vid-Vendor Id Register (Sata-D31:F2)
00000000h NOTES: ® 1. The Intel 6300ESB ICH SATA Controller is not arbitrated as a PCI device, therefore it does not need a master latency timer. ® 2. Refer to the Intel 6300ESB I/O Controller Hub Specification Update for the most up-to-date value of the Revision ID register.
Page 739: Offset 02 - 03H: Did-Device Id Register (Sata-D31:F2)
1 = Enabled. SATA Controller will generate PERR# when a data parity error is detected. VGA Palette Snoop Reserved as ‘0’. Postable Memory Write Reserved as ‘0’. Enable (PMWE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 740 Special Cycle Enable Reserved as ‘0’. (SCE) ® Controls the Intel 6300ESB ICH’s ability to act as a PCI Bus Master Enable master for IDE Bus Master transfers. This bit does not impact (BME) the generation of completions for split transaction commands.
Page 741: Offset 06 - 07H: Sts-Device Status Register (Sata-D31:F2)
(bit 6 of the command register) is Detected (DPD) ® set. For the Intel 6300ESB ICH, this bit may only be set on read completions when there is a parity error. Fast Back-to-Back Reserved as ‘1’.
Page 742: Offset 09H: Pi-Programming Interface (Sata-D31:F2)
01h when Dev 31, Func 0, offset ACh, bit 23 is ‘0’; indicates IDE controller Sub Class Code 04h when Dev 31, Func 0, offset ACh, bit 23 is ‘1’; indicates RAID controller ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 743: Offset 0Bh: Bcc-Base Class Code (Sata-D31:F2)
Hardwired to 00h. The IDE controller is implemented Bus Master Latency internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 744: Offset 10H - 13H: Pcmd_Bar-Primary Command Block Base Address Register (Sata-D31:F2)
Base Address Base address of the I/O space (4 consecutive I/O locations). Reserved Reserved. Resource Type Indicator This bit is set to ‘1’, indicating a request for IO space. (RTE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 745: Offset 18H - 1Bh: Scmd_Bar-Secondary Command Block Base Address Register
Base Address Base address of the I/O space (4 consecutive I/O locations). Reserved Reserved. Resource Type Indicator This bit is set to ‘1’, indicating a request for IO space. (RTE) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 746: Offset 20H - 23H: Bar-Legacy Bus Master Base Address Register (Sata-D31:F2)
The value written to this register will also be readable through the corresponding SVID registers for the USB#1, USB#2 and SMBus functions. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 747: Offset 2Eh - 2Fh: Sid-Subsystem Id (Sata-D31:F2)
Read/Write Offset: Attribute: 8-bit Default Value: Size: Bits Name Description Access It is to communicate to software the interrupt line that the Interrupt Line interrupt pin is connected to. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 748: Offset 3Dh: Intr_Pn-Interrupt Pin Register (Sata-D31:F2)
Reserved. ® The value of 01h indicates to “software” that the Intel 6300ESB ICH will drive INTA#. Note that this is only used in Interrupt Pin native mode. Also note that the routing to the internal interrupt controller does not necessarily relate to the value in this register.
Page 749 Drive 0 Fast Timing Bank this drive. (TIME0) 1 = Accesses to the data port will use bits 13:12 for the IORDY sample point, and bits 9:8 for the recovery time. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 750: Offset 44H: Sidetim-Slave Ide Timing Register (Sata-D31:F2)
IDE timing register for primary is set. Primary Drive 1 00 = 4 clocks Recovery Time (PRCT1) 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 751: Offset 48H: Sdma_Cnt—Synchronous Dma Control Register (Sata–D31:F2)
1 = Enable Synchronous DMA mode for primary channel drive Enable (PSDE1) Primary Drive 0 0 = Disable (default) Synchronous DMA Mode 1 = Enable Synchronous DMA mode for primary channel drive Enable (PSDE0) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 752: Offset 4A - 4Bh: Sdma_Tim-Synchronous Dma Timing Register (Sata-D31:F2)
10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_SCB1 = ’1’ (133MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 753 10 = CT 2 clocks, RP 8 clocks 11 = Reserved FAST_PCB1 = ’1’ (133MHz clk) 00 = Reserved 01 = CT 3 clks, RP 16 clks 10 = Reserved 11 = Reserved ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 754: Offset 54H: Ide_Config-Ide I/O Configuration Register (Sata-D31:F2)
Name Description Access 31:2 Reserved Reserved. ® 23:2 The Intel 6300ESB ICH does not perform any actions on Scratchpad (SP2) these bits. 19:1 Reserved Reserved. 17:1 Reserved Reserved. This bit is used in conjunction with the SCT1 bits to enable/ disable Ultra ATA/100 timings for the Secondary Slave drive.
Page 755: Offset 70 - 71H: Pid-Pci Power Management Capability Id (Sata-D31:F2)
Indicates PME# cannot be generated form the SATA host 15:1 PME_Support controller. When in low power state, resume events are not allowed. D2_Support The D2 state is not supported D1_Support The D1 state is not supported ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 756: Offset 74 - 75H: Pmcs-Pci Power Management Control And Status (Sata-D31:F2)
10: D2 state 11: D3hot state When in the D3hot state, the controller’s configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 757: Offset 80 - 81H: Mid-Message Signaled Interrupt Identifiers (Sata-D31:F2)
Capable of generating 32-bit message only. (C64) Multiple Message Enable These bits are R/W for software compatibility, but only one ® (MME) message is ever sent by the Intel 6300ESB ICH. Multiple Message Only one message is required. Capable (MMC) 0 = Disabled.
Page 758: Offset 84 - 87H: Ma-Message Signaled Interrupt Message Address (Sata-D31:F2)
Read/Write Offset: Attribute: 0000h 32-bit Default Value: Size: Bits Name Description Access Lower 32 bits of the system specified message address, 31:2 Address (ADDR) always DWORD aligned. Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 759: Offset 88 - 89H: Md-Message Signaled Interrupt Message Data (Sata-D31:F2)
P-ATA is secondary. 110 = Combined. P-ATA is primary. P0 is secondary master. P1 is secondary slave. 111 = Combined. P-ATA is primary. P0 is secondary slave. P1 is secondary master. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 760: Offset 92H: Pcs-Port Status And Control (Sata-D31:F2)
Reserved. This field is a 7-bit index pointer into the SATA Registers Index (IDX) space. Data is written into the SRD register (D31:F2:A4h) and read from the SRD register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 761: Offset A4H - A7H: Srd-Sata Registers Data (Sata-D31:F2)
This field is a 32-bit data value that is written to the register 31:0 Data (DTA) pointed to by SRI (D31:F2:A0h) or read from the register pointed to by SRI. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 762: Sttt-Sata Tx Termination Test Register A (Sata-D31:F2)
Name Description Access 15:2 Reserved Reserved. ® This bit will force the Intel 6300ESB ICH to repeatedly Force ALIGN TX Bit transmit the SATA ALIGN primitive when set. This bit is only used for system board testing. Reserved Reserved. ®...
Page 763: Offset Index 54H - 57H: Ser0-Sata Serror Register Port 0 (Sata-D31:F2)
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA– D31:F2) (Sheet 1 of 3) Device: Function: E0h–E3h Read/Write, Read/Write Clear Offset: Attribute: 00000000h 32-bit Default Value: Size: Bits Name Description Access 31:1 Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 764 ® When a rising edge is detected on this bit field, the Intel 6300ESB ICH initiates a BIST FIS to the device on Port 1, using the parameters specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 1 is present and ready (not partial/slumber state).
Page 765: Offset E4H - E7H: Bftd1-Bist Fis Transmit Data1 Register (Sata-D31:F2)
The data programmed into this register will form the contents ® of the second DWord of any BIST FIS initiated by the Intel 6300ESB ICH. This register is not port specific — its contents will be used for BIST FIS initiated on port 0 or port 1.
Page 766: Offset E8H - Ebh: Bftd2-Bist Fis Transmit Data2 Register (Sata-D31:F2)
The data programmed into this register will form the contents ® of the third DWord of any BIST FIS initiated by the Intel 6300ESB ICH. This register is not port specific — its contents will be used for BIST FIS initiated on port 0 or port 1.
Page 767: Bmic[P,S]-Bus Master Ide Command Register (D31:F2)
Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not clear this bit automatically. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 768: Bmis[P,S]-Bus Master Ide Status Register (D31:F2)
It is also cleared by ® the Intel 6300ESB ICH when the Start bit is cleared in Bus Master IDE Active the Command register. When this bit is read as a ’0’, all...
Page 769: Bmid[P,S]-Bus Master Ide Descriptor Table Pointer Register (D31:F2)
Access Corresponds to A[31:2]. The Descriptor Table must be Address of Descriptor 31:2 DWORD-aligned. The Descriptor Table must not cross a 64-K Table (ADDR) boundary in memory. Reserved Reserved. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 770 ® Intel 6300ESB ICH—20 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 771: Ball Diagram (Top View - Left Side)
PXC/BE[5]# Vcc3_3 PXAD[60] Vcc3_3 GPIO[27] SLP_S3# PXAD[59 PXPCIRST GPIO[25 SYSRESE SMLIN SMLIN PXAD[63] PXAD[62] PXAD[57] PXAD[55] SMBCLK K[1] K[0] PXAD[58 GPIO[28 PWRBTN SUSCL SMBD PXAD[61] PXAD[56] PXAD[52] PME# SLP_S5# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 772: Ball Diagram (Top View - Right Side)
PDCS1# SDD[7] SDD[5] PWDMARD SATA[0]TX SATA[1]TX INTRUDER VccSus1_5 Vcc1_5 RTCRST# PDD[1] PDA[1] PDA[0] SATA[0]RX SATA[1]RX SATARBIA SATACLKP Vcc1_5 PDD[6] PDD[11] PDD[2] PDD[15] SATA[0]RX SATA[1]RX SATARBIA SATACLKN RSMRST# PDD[4] PDD[13] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 773: Mechanical Drawing
® 21—Intel 6300ESB ICH Figure 38. Mechanical Drawing ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 774: Signal List (Alphabetical List)
PXIRQ[0]# AD[29] GPIO[34] / AD[30] PXIRQ[1]# AD[31] GPIO[35] / C/BE[0]# PXIRQ[2]# C/BE[1]# GPIO[36] / C/BE[2]# PXIRQ[3]# C/BE[3]# GPIO[37] CLK14 GPIO[38] CLK48 GPIO[39] CPUSLP# GPIO[40] DEVSEL# GPIO[41] FERR# AA29 GPIO[42] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 775 AC22 PDD[11] AH25 PDD[12] AE23 PDD[13] AJ26 PDD[14] AE24 PDD[15] AH27 AD13 PDDACK# AB22 AJ14 PDDREQ AF24 AJ15 PDIOR# (/ PDWSTB / AB21 PRDMARDY#) PDIOW# (/ AB23 PDSTOP) PERR# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 776 PXIRDY# PXAD[26] PXM66EN PXAD[27] PXPAR PXAD[28] PXPAR64 PXAD[29] PXPCICLK PXAD[30] PXPCIRST# PXAD[31] PXPCIXCAP PXAD[32] PXPCLKI PXAD[33] PXPCLKO[0] PXAD[34] PXPCLKO[1] PXAD[35] PXPCLKO[2] PXAD[36] PXPCLKO[3] PXAD[37] PXPCLKO[4] PXAD[38] PXPERR# PXAD[39] PXPLOCK# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 777 AF29 SYSRESET# AH11 SDD[6] THRM# SDD[7] AF28 THRMTRIP# AA28 SDD[8] TRDY# SDD[9] AE26 UART_CLK SDD[10] AB24 USBP0N SDD[11] AC26 USBP0P SDD[12] AE28 USBP1N SDD[13] AB25 USBP1P SDD[14] AD27 USBP2N ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 778 Vcc3_3 VCCPLL3 Vcc3_3 AD24 VCCREF Vcc3_3 VCCREF Vcc3_3 AE11 VCCRTC AC19 Vcc3_3 AE22 VccSus1_5 AE15 Vcc3_3 VccSus1_5 AG15 Vcc3_3 AF21 VccSus1_5 Vcc3_3 VccSus1_5 Vcc3_3 VccSus1_5 Vcc3_3 VccSus1_5 Vcc3_3 VccSus1_5 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 779 AH20 AH22 AH28 AJ16 AJ18 AJ20 AA25 AJ22 AB12 AJ27 AB18 AC11 AC15 AC18 AC24 AC27 AD11 AD12 AD17 AD23 AE13 AE19 AE25 AE27 AF10 AF12 AF14 AF17 AF19 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 780 Package Information Table 706. Signal List (Alphabetical Table 706. Signal List (Alphabetical List) List) Signal Location Signal Location VSWING ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 781: Signal List (By Location)
SDCS3# AC23 IRQ[14] AA28 THRMTRIP# AC24 AA29 FERR# AC25 Vcc3_3 PXAD[47] AC26 SDD[11] PXAD[45] AC27 PXAD[42] AC28 SDD[15] AC29 SDA[2] PXGNT1# PXAD[41] Vcc3_3 PXAD[40] PXAD[44] Vcc3_3 Vcc1_5 PXAD[38] PXAD[54] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 782 AE20 Vcc1_5 AG12 VccSus3_3 AE21 RTCX1 AG13 AE22 Vcc3_3 AG14 SLP_S3# AE23 PDD[12] AG15 VccSus1_5 AE24 PDD[14] AG16 Vcc1_5 AE25 AG17 AE26 SDD[9] AG18 SATA[0]TXN AE27 AG19 AE28 SDD[12] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 783 AH27 PDD[15] AH28 PXAD[61] C/BE[0]# PXAD[58] AD[2] PXAD[56] PXAD[52] Vcc3_3 PME# GPIO[28] AD[15] AJ10 PWRBTN# AJ11 SLP_S5# Vcc3_3 AJ12 SUSCLK AJ13 SMBDATA GNT[2]# AJ14 AJ15 Vcc3_3 AJ16 AJ17 SATACLKN ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 784 Vcc3_3 TRDY# SIU0_CTS# AD[4] SIU1_RI# SIU1_RXD Vcc1_5 GPIO[37] LDRQ[0]# VccSus1_5 GPIO[57] SIU0_RTS# VccSus3_3 VccSus3_3 USBP1P AC_SYNC USBP0N VccSus1_5 AC_SDIN0 USBRBIASN OC[1]# AD[17] OC[0]# AD[10] IRDY# SERR# Vcc3_3 GPIO[38] AD[26] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 785 Vcc3_3 GPIO[35] / GPIO[43] PXIRQ[2]# GPIO[21] Vcc3_3 AD[29] SPKR C/BE[3]# AD[23] PXAD[27] AD[8] PXREQ[0]# Vcc3_3 PXAD[28] AD[0] PXPCLKO[4] AD[28] PXREQ[1]# Vcc1_5 PXPCLKO[1] VccSus3_3 GPIO[23] Vcc1_5 VccSus1_5 GPIO[19] VccSus1_5 CLK14 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 786 Vcc3_3 PXFRAME# PXPCIXCAP Vcc3_3 HI11 PXAD[22] PXAD[20] PXAD[23] PXAD[24] Vcc3_3 VccHI PXC/BE[3]# Vcc1_5 VccHI VccHI PXPLOCK# PXSTOP# PXDEVSEL# Vcc1_5 VccSus1_5 PXTRDY# PXAD[15] VccHI HI10 PXAD[17] PXAD[18] Vcc3_3 PXAD[19] Vcc1_5 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 787 PXAD[3] IGNNE# V_CPU_IO PXAD[43] GPIO[17] / V_CPU_IO PXGNT[3]# GPIO[1] / PXREQ[3]# PXAD[12] PXAD[11] SDD[8] SDDACK# PXAD[13] SDIOW# / (SDSTOP) VCCREF VRMPWRGD PXAD[2] Vcc1_5 INTR IRQ[15] SDA[0] RCIN# CPUSLP# SMI# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 788 ® 21—Intel 6300ESB ICH ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 789: Electrical Characteristics
Functional Operating Range ® All of the AC and DC Characteristics specified in this document assume that the Intel 6300ESB ICH component is operating within the Functional Operating Range given in this section. Operation outside of the Functional Operating Range is not recommended, and extended exposure outside of the Functional Operating Range may affect component reliability.
Page 790: Dc Characteristic Input Signal Association
SMBus Signals: SMBCLK, SMBDATA System Management Signals: INTRUDER#, SMLINK[1:0], SMBALERT#/GPIO[11] Power Management Signals: RSMRST#, RTCRST#, PWROK CPU Signals: FERR#, THRMTRIP# Hub Interface Signals: HI[11:0], HI_STBS, HI_STBF Real Time Clock Signals: RTCX1, RTCX2 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 791: Dc Input Characteristics
7. When probed at the receiver pin of the ICH for data/strobe, the waveform may show a “knee” due to package parasitics. Simulation verifies that this “knee” represents no risk, since a clean waveform is present at the ICH ball input due to internal receiver termination. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 792 7. When probed at the receiver pin of the ICH for data/strobe, the waveform may show a “knee” due to package parasitics. Simulation verifies that this “knee” represents no risk, since a clean waveform is present at the ICH ball input due to internal receiver termination. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 793: Dc Characteristic Output Signal Association
Hub Interface Signals: HI[11:0], HI_STBS, HI_STBF Zpd/Zpu SATA Signals: SATA[1:0]TX[P,N] V HSOI V HSOH V HSOL USB Signals: USBP[3:0][P:N] in High Speed Modes V CHIRPJ V CHIRPK 1. These signals are open drain. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 794: Dc Output Characteristics
2. SATA Vdiff,tx is measured at the SATA connector on the transmit side. Table 713. Other DC Characteristics (Sheet 1 of 2) Symbol Parameter Unit Notes ® Intel 6300ESB ICH Core Well V5REF + 4.75 V5REF Reference Voltage I/O Buffer Voltage 3.135 3.465...
Page 795 Output Capacitance F C = 1 MHz C I/O I/O Capacitance F C = 1 MHz Typical Value XTAL1 XTAL2 NOTES: 1. Includes CLK14, CLK48, HICLK, PCICLK and PXPCICLK. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 796: Clock Timings
Operating Frequency High time Figure 59 Low time Figure 59 Rise time 1000 Figure 59 Fall time Figure 59 AC’97 Clock (BITCLK) f ac97 Operating Frequency 12.288 Output Jitter ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 797 Operating Frequency High Time t40a Low Time UART Clock (UART_CLK) 14.745 Operating Frequency Frequency Tolerance 2500 t10a High Time t11a Low Time t12a Rise Time t13a Fall Time ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 798 1. CLK48 is a 48 MHz clock that expects a 40/60% duty cycle. ® 2. CLK48 is a pass-thru clock that is not altered by the Intel 6300ESB ICH. This frequency tolerance specification is required for USB 2.0 compliance and is affected by external elements such as the clock generator and the system board.
Page 799: Pci-X Interface Timings
In conventional mode, the device must meet the requirements specified in PCI Local Bus Specification, Revision 2.2, for the appropriate clock frequency. 11.Device must meet this specification independent of how many outputs switch simultaneously. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 800: Pci Interface Timing
Figure 4 PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCICLK Rising Figure 4 PXPCIRST# Low Pulse Width GNT[A:B}#, GNT[5:0]# Valid Delay from PCICLK Rising REQ[A:B]#, REQ[5:0]# Setup Timer to PCICLK Rising ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 801: Ide Pio And Multiword Dma Modetiming
4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or greater. Refer to the RCT field in the IDE Timing Register. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 802: Ultra Ata Timing (Mode 0, Mode 1, Mode 2)
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/ ATAPI - 6) specification name. 2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring these timing parameters. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 803 1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/ ATAPI - 6) specification name. 2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring these timing parameters. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 804: Ultra Ata Timing (Mode 3, Mode 4, Mode 5)
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/ ATAPI - 6) specification name. 2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring these timing parameters. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 805 1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/ ATAPI - 6) specification name. 2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring these timing parameters. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 806: Universal Serial Bus Timing
8. Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps. 9. Refer to the latest revision of the Universal Serial Bus Specification for High speed source timings ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 807 8. Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps. 9. Refer to the latest revision of the Universal Serial Bus Specification for High speed source timings ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 808: Smbus Timing
4. t134 has a minimum timing for I C of 0 ns, while the minimum timing for SMBus is 300 ns. ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 809: Ac'97 Timing
SERIRQ Hold Time from PCICLK Rising Figure 46 RI# Pulse Width RTCCLK Figure 48 SPKR Valid Delay from CLK14 Rising Figure 45 SERR# Active to NMI Active IGNNE# Inactive from FERR# Inactive ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 810: Uart Timings
SIU0_RXD, SIU1_RXD Hold Time to UART_CLK Rising SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#, t154a SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI# High Time SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#, t155a SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI# Low Time ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 811: Power Sequencing And Reset Signal Timings
1. The V5Ref supply must power up before or simultaneous with its associated 3.3 V supply, and must power ® down simultaneous with or after the 3.3 V supply. See the Intel 6300ESB ICH Design Guide for details. 2. The associated 3.3 V and 1.5 V supplies must power up or down simultaneously.
Page 812: Power Management Timings
® 4. The Intel 6300ESB ICH has no maximum timing requirement for this transition. It is up to the system designer to determine if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes. 5. If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted together similar to timing t194 (PXPCIRST# active to SLP_S3# active).
Page 813: Pci-X 3.3V Clock
0.5 Vcc 0.4 Vcc, p-to-p 0.4 Vcc (minimum) 0.3 Vcc 0.2 Vcc Figure 40. Clock Uncertainty (PXPCLK[0:4]) Table 729. Clock Uncertainty Parameters Symbol Parameter Units Vtest-clk 0.4Vcc Tskew 0.4(Max) ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 814: Pci-X Output Timing
T_val OUTPUT DELAY V_tfall T_val V_trise OUTPUT DELAY Tri-State OUTPUT T_on T_off Figure 42. PCI-X Input Timing V_th V_test V_tl T_su V_th INPUT V_test inputs valid V_test V_max V_tl ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 815: Pci-X Rst# Timing For Switching To Pci-X Mode Pull-Ups
FRAME# IRDY# TRDY# STOP# DEVSEL# T_prsu T_prh T_rst(ref) 22.5.2 System Clocks and General Timing Figure 44. Clock Timing Period High Time 2.0V 0.8V Low Time Fall Time Rise Time ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 816: Valid Delay From Rising Clock Edge
Valid Delay Output Figure 46. Setup and Hold Times Clock 1.5V Setup Time Hold Time Input Figure 47. Float Delay Clock Float Delay Output Figure 48. Pulse Width Pulse Width ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 817: Output Enable Delay
Delay Output 22.5.3 IDE and Ultra ATA Timing Figure 50. IDE PIO Mode HICLK DIO x DD[15:0] Write Write DD[15:0] Read Read Sample IORDY t62, t63 DA[2:0], CS1# B3925-01 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 818: Ide Multiword Dma
DD[15:0] Write Write Data idedma.v sd Figure 52. Ultra ATA Mode (Drive Initiating a Burst Read) DMARQ (drive) DMACK# (host) STOP (host) DMARDY# (host) t99b STROBE (drive) DD[15:0] DA[2:0], CS[1:0] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 819: Ultra Ata Mode (Sustained Burst)
Data @ sender t99d t99d STROBE @ receiver t99e t99e t99e Data @ receiver Figure 54. Ultra ATA Mode (Pausing a DMA Burst) STOP (host) DMARDY# STROBE DATA ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 820: Ultra Ata Mode (Terminating A Dma Burst)
= 50 pF, 300 ns at C = 350 pF Full Speed: 4 to 20 ns at C = 50 pF = 10 pF High Speed: 0.8 to 1.2 ns at C ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 821: Usb Jitter
Paired Transitions Figure 58. USB EOP Width Tperiod Data Crossover Differential Level Data Lines Width 22.5.5 SMBus Figure 59. SMBus Transaction SMBCLK t135 t133 t131 t134 t132 SMBDATA t130 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 822: Smbus Timeout
Power and Reset Figure 61. Power Sequencing and Reset Signal Timings PWROK T175 T176 Vcc3_3, Vcc1_5, VccHI T174 V5Ref RSMRST# T172 T173 VccSus3_3, VccSus1_5 T171 V5RefSus RTCRST# T170 VccRTC ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 823: G3 (Mechanical Off) To S0 Timings
SLP_S5# Running SUSCLK T182 RSMRST# T173 VccSus Figure 63. S0 to S1 to S0 Timing STATE STPCLK# T190 PCI Stop Grant Cycle T187 CPUSLP# T188 T189 Wake Event ich2_S0_S1D_timing.vsd ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 824: S0 To S5 To S0 Timings
T194a SLP_S5# T195 T198d Wake Event PWROK, VRMPWRGD T196 T176 T197 22.5.7 AC’97 and Miscellaneous Figure 65. AC’97 Data Input and Output Timings setup AC_BIT_CLK AC_SDOUT AC_SDIN[2:0] AC_SYNC hold ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 825: Testability
® The Intel 6300ESB ICH supports two types of test modes, a tri-state test mode and a XOR Chain test mode. Driving RTCRST# low for a specific number of PCI clocks while PWROK is high will activate a particular test mode as described in Table 731.
Page 826: Test Mode Entry (Xor Chain Example)
23.3 XOR Chain Mode ® In the Intel 6300ESB ICH, provisions for Automated Test Equipment (ATE) board level ® testing are implemented with XOR Chains. The Intel 6300ESB ICH signals are grouped into seven independent XOR chains which are enabled individually. When an XOR chain is enabled, all output and bi-directional buffers within that chain are tri- stated, except for the XOR chain output.
Page 827: Xor Chain #1
PXC/BE[1]# GPIO[33] / PXIRQ[0]# PXPAR GPIO[34] / PXIRQ[1]# PXPERR# GPIO[35] / PXIRQ[2]# PXC/BE[0]# GPIO[36] / PXIRQ[3]# RASERR# PXREQ[1]# PXREQ64# GPIO[0] / PXREQ[2]# PXACK64# PXGNT0# OUTPUT IRQ[14] AC23 PXIRDY# PXFRAME# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 828: Xor Chain #2
AG27 TRDY# PDA[0] AG28 FRAME# PDCS1# AF27 AD[7] PDA[2] AA23 AD[9] PDCS3# AD25 AD[2] REQ[2]# REQ[3]# AD[5] GNT[3]# AD[13] GNT[2]# AD[1] GPIO[2] / PIRQ[E]# SERR# GPIO[3] / PIRQ[F]# C/BE[0]# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 829: Xor Chain #3
SPKR Pin Name Ball # SATALED# IRQ[15] GPIO[40] GPIO[18] VRMPWRGD GPIO[19] A20GATE AB29 RCIN# GPIO[20] GPIO[21] THRMTRIP# AA28 GPIO[23] FERR# AA29 GPIO[42] A20M# GPIO[38] INTR GPIO[43] GPIO[41] IGNNE# INIT# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 830 AC_BIT_CLK AC_SYNC AC_SDOUT GPIO[6] GPIO[7] OUTPUT IRQ[14] AC23 GPIO[39] GPIO[37] SERIRQ SIU1_RXD SIU1_TXD SIU1_CTS# SIU1_DSR# SIU1_DCD# SIU1_RI# SIU1_DTR# SIU1_RTS# UART_CLK SIU0_RXD SIU0_TXD SIU0_CTS# SIU0_DSR# SIU0_DCD# SIU0_RI# SIU0_DTR# SIU0_RTS# LAD[0] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 831: Xor Chain #4
SMBCLK AH14 PXC/BE[3]# GPIO[11] / SMBALERT# AF15 PXAD[24] AJ14 PXAD[23] AJ15 PXAD[20] OC[0]# PXAD[22] OC[2]# PXAD[21] OC[1]# PXAD[19] OC[3]# PXAD[18] AC_SDIN0 PXAD[17] AC_RST# PXAD[16] AC_SDIN2 PXC/BE[2]# AC_SDIN1 PXPLOCK# PXDEVSEL# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 832 GPIO[1] / PXREQ[3]# PXAD[52] PXGNT1# SDD[7] AF28 PXPCLKI SDD[9] AE26 PXPCICLK SDD[5] AF29 PCIXSBRST# SDD[8] PXAD[44] SDD[3] AD26 PXAD[35] SDD[6] PXAD[38] SDD[10] AB24 PXAD[32] SDD[12] AE28 PXAD[34] SDD[11] AC26 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 833 SDDACK# SIORDY / (SDRSTB/ SWDMARDY#) SDA[1] AD29 SDD[15] AC28 SDD[2] AB27 SDA[2] AC29 SDIOW# / (SDSTOP) SDD[0] AA26 SDCS1# AB28 SDIOR# / (SDWSTB/ PRDMARDY#) SDCS3# AA27 SDA[0] OUTPUT IRQ[15] ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 834 Pin Name Ball # SATACLKN AJ17 SATACLKP AH17 SATA[0]RXN AJ19 SATA[0]RXP AH19 SATA[0]TXN AG18 SATA[0]TXP AF18 SATA[1]RXN AJ21 SATA[1]RXP AH21 SATA[1]TXN AG20 SATA[1]TXP AF20 SATARBIASN AJ23 SATARBIASP AH23 OUTPUT LDRQ[1]# ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 835: Index
Base and Current Address 348 Base and Current Count 349 Base Class Code 441, 743 Binary/BCD Countdown Select 356 BIOS_EN 407 BIOS_RLS BIOS Release 406 BIOS_STS 409 BIOSWR_STS 419 BIST FIS Failed 764 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 836: Ds November
Counter 0 Select 357 Counter 1 Select 357 Counter 2 Select 357 Counter Latch Command 358 Counter OUT Pin State 359 Counter Port 360 Counter Select 356 Counter Selection 358 COUNTER_CLK_PER_CAP 606 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 837 Drive 0 Fast Timing Bank (TIME0) 450, 749 Drive 0 IORDY Sample Point Enable (IE0) 450, 749 Drive 0 Prefetch/Posting Enable (PPE0) 450, 749 Drive 1 DMA Capable 457, 768 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 838 Frame List Size 510 FREQ_STRAP 330 FULL_RST 383 FWH_C0_EN 336, 342 FWH_C0_IDSEL 339 FWH_C8_EN 336, 342 FWH_C8_IDSEL 339 FWH_D0_EN 336, 342 FWH_D0_IDSEL 339 FWH_D8_EN 335, 342 FWH_D8_IDSEL 339, 341 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 839 Host System Error Enable. 514 HOST_BUSY 536 HOST_NOTIFY_INTREN 546 HOST_NOTIFY_STS 546 HOST_NOTIFY_WKEN 546 HOURFORM Hour Format 379 HST_EN SMBus Host Enable 533 HUBNMI_STS 419 HUBSCI_STS 419 HUBSERR_STS 419 HUBSMI_STS 419 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 840 IRQ12_CAUSE 424 IRQ12LEN Mouse IRQ12 Latch Enable 328 IRQ14 ECL 367 IRQ15 ECL 367 IRQ1LEN Keyboard IRQ1 Latch Enable 328 IRQ3 ECL 367 IRQ4 ECL 367 IRQ5 ECL 367 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 841 MD3 575, 603 Memory Space (MS) 552 Memory Space Enable (MSE) 437, 740 Mic In Interrupt (MINT) 576, 604 Microphone 2 In Interrupt (M2INT) 575, 602 Microprocessor Mode 364 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 842 PCM 4/6 Enable 573 452, 751 PCM In 1, Microphone In 1 Data In Line (DI1L) 578 Primary Drive 1 Cycle Time (PCT1) 454, 753 PCM In 2 Interrupt (P2INT) 575, 602 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 843 RW 539 S/PDIF Interrupt (SPINT) 575, 602 SAFE_MODE 329 Sample Capabilities 575, 602 SATA Setup Data A 762 SATA Setup Data B 762 SB16 Decode Range 334 SB16_LPC_EN 338 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 844 SMI on CF Enable 502 SMI on Frame List Rollover 500 SMI on Frame List Rollover Enable 501 SMI on HCHalted 502 SMI on HCHalted Enable 502 SMI on HCReset 502 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 845 SWSMI_TMR_EN Software SMI# Timer Enable 406 SWSMI_TMR_STS 409 SYS_RST 383 System Reset Status (SRS) 386 T00_INT_STS 608 T01_INT_STS 608 T02_INT_STS 608 TCO_EN 406 TCO_INT_STS 420 TCO_MESSAGE 423 TCO_STS 408 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 846 USB Error Interrupt Enable 514 USB Interrupt 513 USB Interrupt (USBINT) 479 USB Interrupt Enable 514 USB_ADDRESS_CNF USB_ENDPOINT_CNF 526 USB1_EN 405 USB1_STS 403 USB2.0 Controller (D29 F7) 221 USB2_EN 405 USB2_STS 403 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 847 Vendor ID Value 527 VENDOR_ID_CAP 606 VRT Valid RAM and Time Bit 380 WAK_STS 394 WDSTATUS Watchdog Status 424 Write Policies for Periodic DMA 225 WRITE_READ#_CNT 524 WRT_RDONLY 503 ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...
Page 848 ® Intel 6300ESB ICH— ® Intel 6300ESB I/O Controller Hub November 2007 Order Number: 300641-004US...

Intel 6300ESB Datasheet

Table of Contents

Table of Contents

Table of Contents

Table of Contents

3.18 Universal Asynchronous Receive and Transmit (Uart0,1)

3.17 AC'97 Link

3.18 Universal Asynchronous Receive and

5.18.11.2.2In Transactions

USB UHCI Controllers Registers

AC'97 Modem Controller Registers (D31:F6)

PCI-X Overview (D28:F0)

Serial I/O Unit

Package Information

Electrical Characteristics

Testability

Quick Links

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Summary of Contents for Intel 6300ESB