Power Management; Sys_Reset# Usage Model; Pwrbtn# Usage Model; Power-Well Isolation Control Strap Requirements - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Intel 6300ESB Design Guidelines
9.15

Power Management

9.15.1

SYS_RESET# Usage Model

The System Reset ball (SYS_RESET#) on the 6300ESB may be connected directly to the reset
button on the system front panel, provided that the front panel header pulls this signal up to 3.3 V
standby through a weak pull-up resistor. The 6300ESB will debounce signals on this pin (16 ms)
and allow the SMBus to go idle before resetting the system. This helps to prevent a slave device on
the SMBus from hanging by resetting in the middle of a cycle.
Note: The PWORK signal should not be used to implement front panel reset.
9.15.2

PWRBTN# Usage Model

The Power Button ball (PWRBTN#) on the 6300ESB may be connected directly to the power
button on the system front panel. This signal is internally pulled-up in the 6300ESB to 3.3 V
standby through a pull-up resistor (24 K Ω nominal). The 6300ESB has 16 ms of internal debounce
logic on this pin.
Figure 135.

SYS_RESET# and PWRBTN# Connection

Note: SYS_RESET# IS 3.3 V tolerant and should be pulled up to 3.3 V standby the the front panel header.
9.15.3

Power-Well Isolation Control Strap Requirements

Note: The RSMRST# signal of the 6300ESB must transition from 20% signal level to 80% signal level
and vice-versa within 50uS.
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6300ESB ICH Embedded Platform Design Guide
ATX
Power
Supply
PWRGD_PS
Level
Shifter
Front
Panel
Header
MCH
RSTIN#
PWROK
SYS_RESET#
PWRBTN#
PCIRST#
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Intel 6300ESB
I/O Controller Hub
FWH
RST
SIO
PCI_RESET
B2899-01