Pirq Routing Example; Ioapic Interrupt Inputs 16 Through 23 Usage - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
9.9.2

PIRQ Routing Example

Table 93
Table 93.

IOAPIC Interrupt Inputs 16 through 23 Usage

No
1
2
3
4
5
6
7
8
Due to different system configurations, IRQ line routing to the PCI slots (swizzling) should be
made to minimize the sharing of interrupts between both internal 6300ESB functions and PCI
functions. The figure below shows an example of IRQ line routing to the PCI slots
It is not necessarily an optimal routing scheme; an optimal scheme depends on individual system
PCI IRQ usage.
Figure 121. Example PIRQ Routing
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Intel
I/O Controller
NOTE: This figure is an example; it is up to the board designer to route these signals in the most efficient
manner for their particular system. A PCI slot can be routed to share interrupts with any of the Intel
6300ESB I/O Controller Hub's internal devices/functions, but at a higher latency cost.
shows how the 6300ESB uses the PCI IRQ when the IOAPIC is active.
IOAPIC INTIN PIN
IOAPIC INTIN PIN 16 (PIRQA) USB UHCI Controller #1
IOAPIC INTIN PIN 17 (PIRQB) AC'97 Audio and Modem; option for SMBus
IOAPIC INTIN PIN 18 (PIRQC) USB UHCI Controller #3; Native mode SATA/IDE
IOAPIC INTIN PIN 19 (PIRQD) USB UHCI Controller #2
IOAPIC INTIN PIN 20 (PIRQE) Option for SCI, TCO, MMT #0,1,2
IOAPIC INTIN PIN 21 (PIRQF) Option for SCI, TCO, MMT #0,1,2
IOAPIC INTIN PIN 22
(PIRQG)
IOAPIC INTIN PIN 23 (PIRQH) USB EHCI Controller, Option for SCI, TCO, MMT #0,1,2
PIRQA#
PIRQB#
PIRQC#
PIRQD#
6300ESB
Hub
PIRQE#
PIRQF#
PIRQG#
PIRQH#
SLOT 1
PCI Device 0
(AD16 to IDSEL)
January 2007
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6300ESB ICH Embedded Platform Design Guide
Intel
Function in 6300ESB using the PCI IRQ in IOAPIC
Option for SCI, TCO, MMT #0,1,2
INTA INTA
INTB INTB
INTC INTC
INTD INTD
SLOT 2
PCI Device 5
(AD21 to IDSEL)
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6300ESB Design Guidelines
INTA INTA
INTB INTB
INTC INTC
INTD INTD
SLOT 3 SLOT 4
PCI Device 6 PCI Device C
(AD22 to IDSEL) (AD28 to IDSEL)
B2897-01
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