Table Of Contents - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Contents
1 Introduction..................................................................................................................................21
1.1 Reference Documents ........................................................................................................23
2 System Overview ......................................................................................................................... 25
2.1 Terminology ........................................................................................................................ 25
2.2 System Features................................................................................................................. 25
2.3 Component Features .......................................................................................................... 27
2.3.1 Intel
2.3.1.1
2.3.1.2
2.3.2 Intel
2.3.3 Intel
2.3.4 Intel
2.3.5 ULV Intel
2.3.6 Intel
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
2.3.7 Intel
2.3.8 Firmware Hub (FWH)............................................................................................. 31
2.3.8.1
3 General Design Considerations .................................................................................................33
3.1 Nominal Board Stack-Up .................................................................................................... 33
3.2 Alternate Stack-Ups ............................................................................................................ 35
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4 Intel Pentium
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4.1 Intel Pentium
4.1.1 Recommended Stack-Up Routing and Spacing Assumptions............................... 37
4.1.1.1
4.1.1.2
4.1.1.3
4.1.1.4
4.1.2 Common Clock Signals ......................................................................................... 40
4.1.2.1
4.1.3 Source Synchronous Signals General Routing Guidelines.................................... 42
4.1.3.1
4.1.3.2
4.1.3.3
4.1.4 Length Matching Constraints ................................................................................. 55
4.1.4.1
4.1.4.2
4.1.5 Asynchronous Signals ........................................................................................... 58
4.1.5.1
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Pentium M Processor ................................................................................ 27
Architectural Features ............................................................................ 27
Packaging/Power ................................................................................... 27
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Pentium M Processor on 90 nm Process with 2 MB L2 Cache ................. 27
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Celeron M Processor ................................................................................. 28
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Celeron M Processor on 90 nm process ................................................... 28
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Celeron M Processor at 600 MHz...................................................... 28
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855GME Chipset Graphics Memory Controller Hub (82855GME) ..............29
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Intel Pentium
Integrated System Memory DRAM Controller........................................29
Internal Graphics Controller ................................................................... 29
Packaging/Power ................................................................................... 31
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6300ESB System Features.......................................................................... 31
Packaging/Power ................................................................................... 32
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M/Celeron M Processor FSB Design and Power Delivery Guidelines ...... 37
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M/Celeron M Processor FSB Design Recommendations....................... 37
Trace Space to Trace - Reference Plane Separation Ratio .................. 37
Trace Space to Trace Width Ratio ......................................................... 38
Recommended Stack-up Calculated Coupling Model ........................... 38
Signal Propagation Time-to-Distance Relationship and Assumptions ... 39
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Intel Pentium
Package Length Compensation ............................................................. 41
Source Synchronous - Data Group ....................................................... 47
Source Synchronous - Address Group ................................................. 48
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Intel Pentium
GMCH (82855GME) FSB Signal Package Lengths............................... 49
Package Length Compensation ............................................................. 56
Trace Length Equalization Procedures .................................................. 56
Topology 1A: Open Drain (OD) Signals Driven by the Intel
Pentium M/Celeron M Processor - IERR# ............................................ 59
6300ESB ICH Embedded Platform Design Guide
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M Processor/Intel Celeron
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M/Celeron M Processor Common Clock Signal
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M/Celeron M Processor and Intel
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M Processor Support .... 29
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855GME Chipset
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