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®
Intel
855GME Chipset and Intel
12.4.5
GPIO Checklist
Table 136.
GPIO Checklist
Checklist Items
GPIO Pins
GPIO Pins
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
GPI[0:7]:
These pins are in the Core Power Well.
These signals are inputs thus they need to be pulled up.
Unused core well inputs must be pulled up to V
Pull-ups (8.2 K Ω ) must use the V
Pull-ups (2.7 K Ω ) must use the V
GPI[0:1] may be used as REQ[2:3]#.
GPI[2:5] may be used as PIRQ[E:H]#.
Signals GPI[0:5] are 5 V tolerant
GPI[8] & GPI [11:13]:
These pins are in the Resume Power Well. Pull-ups (8.2 K Ω ) must use
the V
SUS3.3 plane.
CC
These signals are inputs thus they need to be pulled up.
Unused resume well inputs must be pulled up to V
These signals are NOT 5 V tolerant.
GPO[16:23]:
These pins are in the Core Power Well
Fixed as output only. May be left NC.
GPO[16:17] may be used as GNT[2:3]#.
These signals are NOT 5 V tolerant.
GPO[24,25,27,28]:
I/O pins. Default as outputs so may be left as NC.
These pins are in the Resume Power Well.
GPIO[24,25, 28:27] From resume power well. ( Note: Use 8.2 K Ω pull-
up to V
3.3 when these signals are pulled-up).
CCSus
NOTE: These signals are NOT 5 V tolerant.
GPIO[32:43]:
I/O pins. From core power well.
Default as outputs so may be left as NC.
GPIO[32] may be used as WDT_TOUT#
GPIO[33:36] may be used as PXIRQ[0:3]#
GPIO[40:43] these GPIOs have High Strength Output Capability (for
driving LEDs)
These signals are NOT 5 V tolerant.
GPIO[56:57]:
Output pins. From Resume power well.
These are OD signals, use 8.2 K Ω pull-ups to V
January 2007
Schematic Checklist Summary
3.3 or V
5.
CC
CC
3.3 plane.
CC
5 plane.
CC
Sus3.3.
CC
3.3
CCSus
Reason/Impact
Ensure ALL
unconnected
signals are
OUTPUTS
ONLY!
Ensure ALL
unconnected
signals are
OUTPUTS
ONLY!
289
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